From 2d12f6689ca6e8ff7757f8345a2a30e4f5a27d3e Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Fri, 19 Aug 2016 14:44:48 -0700 Subject: [PATCH] make CLOCK_PERIOD actually be the clock period, instead of half of the clock period --- vsim/Makefrag | 2 +- vsrc/TestDriver.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/vsim/Makefrag b/vsim/Makefrag index 2a129ee8..f4bcb7a5 100644 --- a/vsim/Makefrag +++ b/vsim/Makefrag @@ -39,7 +39,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1 $(RISCV)/lib/libfesvr.so \ -sverilog \ +incdir+$(generated_dir) \ - +define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \ + +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ +define+PRINTF_COND=$(TB).printf_cond \ +define+STOP_COND=!$(TB).reset \ +define+RANDOMIZE \ diff --git a/vsrc/TestDriver.v b/vsrc/TestDriver.v index 92d61812..8ddcb22c 100644 --- a/vsrc/TestDriver.v +++ b/vsrc/TestDriver.v @@ -5,7 +5,7 @@ module TestDriver; reg clk = 1'b0; reg reset = 1'b1; - always #`CLOCK_PERIOD clk = ~clk; + always #(`CLOCK_PERIOD/2.0) clk = ~clk; initial #777.7 reset = 0; // Read input arguments and initialize