riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

parameterize number of SCRs

Browse Source
This commit is contained in:
Yunsup Lee 2013-08-24 15:47:14 -07:00
parent de313d97de
commit 2ca5127785
1 changed files with 3 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
rocket/src/main/scala/htif.scala
View File

@ -35,16 +35,15 @@ class HTIFIO(ntiles: Int) extends Bundle
val ipi_rep = (new FIFOIO) { Bool() }.flip val ipi_rep = (new FIFOIO) { Bool() }.flip
} }
class SCRIO extends Bundle class SCRIO(n: Int) extends Bundle
{ {
val n = 64
val rdata = Vec(n) { Bits(INPUT, 64) } val rdata = Vec(n) { Bits(INPUT, 64) }
val wen = Bool(OUTPUT) val wen = Bool(OUTPUT)
val waddr = UFix(OUTPUT, log2Up(n)) val waddr = UFix(OUTPUT, log2Up(n))
val wdata = Bits(OUTPUT, 64) val wdata = Bits(OUTPUT, 64)
} }
class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent
{ {
implicit val (ln, co) = (conf.ln, conf.co) implicit val (ln, co) = (conf.ln, conf.co)
val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client
@ -52,7 +51,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Component
val host = new HostIO(w) val host = new HostIO(w)
val cpu = Vec(nTiles) { new HTIFIO(nTiles).flip } val cpu = Vec(nTiles) { new HTIFIO(nTiles).flip }
val mem = new TileLinkIO val mem = new TileLinkIO
val scr = new SCRIO val scr = new SCRIO(nSCR)
} }
val short_request_bits = 64 val short_request_bits = 64