From 2ca5127785f66cf18aceff7f58511983e0ca2878 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Sat, 24 Aug 2013 15:47:14 -0700 Subject: [PATCH] parameterize number of SCRs --- rocket/src/main/scala/htif.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index 583e90ce..27a79063 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -35,16 +35,15 @@ class HTIFIO(ntiles: Int) extends Bundle val ipi_rep = (new FIFOIO) { Bool() }.flip } -class SCRIO extends Bundle +class SCRIO(n: Int) extends Bundle { - val n = 64 val rdata = Vec(n) { Bits(INPUT, 64) } val wen = Bool(OUTPUT) val waddr = UFix(OUTPUT, log2Up(n)) val wdata = Bits(OUTPUT, 64) } -class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent +class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent { implicit val (ln, co) = (conf.ln, conf.co) val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client @@ -52,7 +51,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Component val host = new HostIO(w) val cpu = Vec(nTiles) { new HTIFIO(nTiles).flip } val mem = new TileLinkIO - val scr = new SCRIO + val scr = new SCRIO(nSCR) } val short_request_bits = 64