riscv/rocket-chip
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Fix paddrBits < xLen && paddrBits == vaddrBits case

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Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
This commit is contained in:
Andrew Waterman 2017-10-09 16:48:04 -07:00
parent 0e6aa7ae9d
commit 2c4009a138
1 changed files with 3 additions and 1 deletions
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4
src/main/scala/tile/BaseTile.scala
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@ -48,7 +48,9 @@ trait HasTileParameters {
require(v == xLen || xLen > v && v > paddrBits) require(v == xLen || xLen > v && v > paddrBits)
v v
} else { } else {
paddrBits min xLen // since virtual addresses sign-extend but physical addresses
// zero-extend, make room for a zero sign bit for physical addresses
(paddrBits + 1) min xLen
} }
def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
def vpnBits: Int = vaddrBits - pgIdxBits def vpnBits: Int = vaddrBits - pgIdxBits