From 2c4009a138ca68f48eb0cbcccb502882f53190b3 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Mon, 9 Oct 2017 16:48:04 -0700
Subject: [PATCH] Fix paddrBits < xLen && paddrBits == vaddrBits case

Require and/or force vaddrBits to be bigger than paddrBits so there's
room to zero-extend a physical address by 1 bit, so that when the virtual
address is sign-extended, the sign is zero.
---
 src/main/scala/tile/BaseTile.scala | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala
index 71e3f909..d6c907fc 100644
--- a/src/main/scala/tile/BaseTile.scala
+++ b/src/main/scala/tile/BaseTile.scala
@@ -48,7 +48,9 @@ trait HasTileParameters {
       require(v == xLen || xLen > v && v > paddrBits)
       v
     } else {
-      paddrBits min xLen
+      // since virtual addresses sign-extend but physical addresses
+      // zero-extend, make room for a zero sign bit for physical addresses
+      (paddrBits + 1) min xLen
     }
   def paddrBits: Int = p(SharedMemoryTLEdge).bundle.addressBits
   def vpnBits: Int = vaddrBits - pgIdxBits