riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

final touches

Browse Source
This commit is contained in:
Yunsup Lee 2014-09-12 00:19:29 -07:00
parent 275b72368b
commit 2c33852c52
2 changed files with 3 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
README.md
View File

@ -32,29 +32,22 @@ To build the VCS simulator:
in either case, you can run a set of assembly tests or simple benchmarks: in either case, you can run a set of assembly tests or simple benchmarks:
$ make run-asm-tests $ make run-asm-tests
$ make run-vecasm-tests
$ make run-vecasm-timer-tests
$ make run-bmarks-test $ make run-bmarks-test
To build a C simulator that is capable of VCD waveform generation: To build a C simulator that is capable of VCD waveform generation:
$ cd emulator $ cd emulator
$ make emulator-debug $ make debug
(note that you must have run `make emulator` at least once before
running `make emulator-debug`)
And to run the assembly tests on the C simulator and generate waveforms: And to run the assembly tests on the C simulator and generate waveforms:
$ make run-asm-tests-debug $ make run-asm-tests-debug
$ make run-vecasm-tests-debug
$ make run-vecasm-timer-tests-debug
$ make run-bmarks-test-debug $ make run-bmarks-test-debug
To get FPGA-synthesizable verilog (output will be in `fsim/generated-src`): To get FPGA-synthesizable verilog (output will be in `fsim/generated-src`):
$ cd fsim $ cd fsim
$ make $ make verilog
Updating To A Newer Version Of Chisel Updating To A Newer Version Of Chisel

3
project/build.scala
View File

@ -30,8 +30,7 @@ object BuildSettings extends Build {
lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel) lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat)
lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore)
lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket)
lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha)
val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")