From 2c33852c525909290efb1fc1aa7a91987672b6b4 Mon Sep 17 00:00:00 2001 From: Yunsup Lee Date: Fri, 12 Sep 2014 00:19:29 -0700 Subject: [PATCH] final touches --- README.md | 11 ++--------- project/build.scala | 3 +-- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/README.md b/README.md index 0cc9e56f..4400a29d 100644 --- a/README.md +++ b/README.md @@ -32,29 +32,22 @@ To build the VCS simulator: in either case, you can run a set of assembly tests or simple benchmarks: $ make run-asm-tests - $ make run-vecasm-tests - $ make run-vecasm-timer-tests $ make run-bmarks-test To build a C simulator that is capable of VCD waveform generation: $ cd emulator - $ make emulator-debug - -(note that you must have run `make emulator` at least once before -running `make emulator-debug`) + $ make debug And to run the assembly tests on the C simulator and generate waveforms: $ make run-asm-tests-debug - $ make run-vecasm-tests-debug - $ make run-vecasm-timer-tests-debug $ make run-bmarks-test-debug To get FPGA-synthesizable verilog (output will be in `fsim/generated-src`): $ cd fsim - $ make + $ make verilog Updating To A Newer Version Of Chisel diff --git a/project/build.scala b/project/build.scala index 250b7f3f..a7b5297a 100644 --- a/project/build.scala +++ b/project/build.scala @@ -30,8 +30,7 @@ object BuildSettings extends Build { lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel) lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(hardfloat) lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore) - lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(uncore, rocket) - lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket, hwacha) + lazy val rocketchip = Project("rocketchip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket) val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code") val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")