riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

previous bug fix for meta data writeback wasn't quite right

Browse Source
This commit is contained in:
Yunsup Lee 2015-03-12 15:34:20 -07:00
parent 5e40c8ba77
commit 2c31ed6426
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
uncore/src/main/scala/cache.scala
View File

@ -868,9 +868,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
is(s_inner_grant) { is(s_inner_grant) {
io.inner.grant.valid := Bool(true) io.inner.grant.valid := Bool(true)
when(ignt_data_done) { when(ignt_data_done) {
val coh_dirty = pending_coh_on_ignt != xact_meta.coh val meta_dirty = !is_hit || pending_coh_on_ignt != xact_meta.coh
when(coh_dirty) { pending_coh := pending_coh_on_ignt } when(meta_dirty) { pending_coh := pending_coh_on_ignt }
state := Mux(!is_hit || coh_dirty, s_meta_write, state := Mux(meta_dirty, s_meta_write,
Mux(io.ignt().requiresAck(), s_inner_finish, s_idle)) Mux(io.ignt().requiresAck(), s_inner_finish, s_idle))
} }
} }