Make prefetch type available in a_type, issue probeInvalidates for putPrefetches

uncore/src/main/scala/broadcast.scala

@@ -219,7 +219,7 @@ class BroadcastAcquireTracker(trackerId: Int)
   val coh = ManagerMetadata.onReset
 
   assert(!(state != s_idle && xact.isBuiltInType() && 
-      Vec(Acquire.putAtomicType, Acquire.prefetchType).contains(xact.a_type)),
+      Vec(Acquire.putAtomicType, Acquire.getPrefetchType, Acquire.putPrefetchType).contains(xact.a_type)),
     "Broadcast Hub does not support PutAtomics or prefetches") // TODO
 
   val release_count = Reg(init=UInt(0, width = log2Up(io.inner.tlNCachingClients+1)))

uncore/src/main/scala/cache.scala

@@ -663,10 +663,11 @@ class L2AcquireTracker(trackerId: Int)(implicit p: Parameters) extends L2XactTra
     val allowedTypes = List((Acquire.getType, Acquire.getType),
                        (Acquire.putType, Acquire.putType),
                        (Acquire.putBlockType, Acquire.putBlockType),
-                       (Acquire.prefetchType, Acquire.prefetchType),
+                       (Acquire.getPrefetchType, Acquire.getPrefetchType),
-                       (Acquire.prefetchType, Acquire.getType),
+                       (Acquire.putPrefetchType, Acquire.putPrefetchType),
-                       (Acquire.prefetchType, Acquire.putType),
+                       (Acquire.getPrefetchType, Acquire.getType),
-                       (Acquire.prefetchType, Acquire.putBlockType))
+                       (Acquire.putPrefetchType, Acquire.putType),
+                       (Acquire.putPrefetchType, Acquire.putBlockType))
     allowedTypes.map { case(a, b) => xact.isBuiltInType(a) && sec.isBuiltInType(b) }.reduce(_||_) &&
       xact_op_code === sec.op_code() &&
       sec.conflicts(xact_addr_block) &&

uncore/src/main/scala/coherence.scala

@@ -186,6 +186,8 @@ class MICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
         Acquire.putBlockType -> probeInvalidate,
         Acquire.getType -> probeCopy, 
         Acquire.putType -> probeInvalidate,
+        Acquire.getPrefetchType -> probeCopy,
+        Acquire.putPrefetchType -> probeInvalidate,
         Acquire.putAtomicType -> probeInvalidate)), 
       probeInvalidate)
 
@@ -286,6 +288,8 @@ class MEICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
         Acquire.putBlockType -> probeInvalidate,
         Acquire.getType -> probeCopy, 
         Acquire.putType -> probeInvalidate,
+        Acquire.getPrefetchType -> probeCopy,
+        Acquire.putPrefetchType -> probeInvalidate,
         Acquire.putAtomicType -> probeInvalidate)),
       probeInvalidate)
 
@@ -397,6 +401,8 @@ class MSICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
         Acquire.putBlockType -> probeInvalidate,
         Acquire.getType -> probeCopy, 
         Acquire.putType -> probeInvalidate,
+        Acquire.getPrefetchType -> probeCopy,
+        Acquire.putPrefetchType -> probeInvalidate,
         Acquire.putAtomicType -> probeInvalidate)),
       MuxLookup(a.a_type, probeCopy, Array(
         acquireShared -> probeDowngrade,
@@ -515,6 +521,8 @@ class MESICoherence(dir: DirectoryRepresentation) extends CoherencePolicy(dir) {
         Acquire.putBlockType -> probeInvalidate,
         Acquire.getType -> probeCopy, 
         Acquire.putType -> probeInvalidate,
+        Acquire.getPrefetchType -> probeCopy,
+        Acquire.putPrefetchType -> probeInvalidate,
         Acquire.putAtomicType -> probeInvalidate)),
       MuxLookup(a.a_type, probeCopy, Array(
         acquireShared -> probeDowngrade,
@@ -654,6 +662,8 @@ class MigratoryCoherence(dir: DirectoryRepresentation) extends CoherencePolicy(d
         Acquire.putBlockType -> probeInvalidate,
         Acquire.getType -> probeCopy, 
         Acquire.putType -> probeInvalidate,
+        Acquire.getPrefetchType -> probeCopy,
+        Acquire.putPrefetchType -> probeInvalidate,
         Acquire.putAtomicType -> probeInvalidate)),
       MuxLookup(a.a_type, probeCopy, Array(
         acquireShared -> probeDowngrade,

uncore/src/main/scala/tilelink.scala

@@ -194,7 +194,8 @@ trait HasAcquireType extends HasTileLinkParameters {
   def isSubBlockType(dummy: Int = 0): Bool = isBuiltInType() && Acquire.typesOnSubBlocks.contains(a_type) 
 
   /** Is this message a built-in prefetch message */
-  def isPrefetch(dummy: Int = 0): Bool = isBuiltInType() && is(Acquire.prefetchType) 
+  def isPrefetch(dummy: Int = 0): Bool = isBuiltInType() &&
+                                           (is(Acquire.getPrefetchType) || is(Acquire.putPrefetchType))
 
   /** Does this message contain data? Assumes that no custom message types have data. */
   def hasData(dummy: Int = 0): Bool = isBuiltInType() && Acquire.typesWithData.contains(a_type)
@@ -314,12 +315,13 @@ class SecondaryMissInfo(implicit p: Parameters) extends TLBundle
 object Acquire {
   val nBuiltInTypes = 5
   //TODO: Use Enum
-  def getType       = UInt("b000") // Get a single beat of data
+  def getType         = UInt("b000") // Get a single beat of data
-  def getBlockType  = UInt("b001") // Get a whole block of data
+  def getBlockType    = UInt("b001") // Get a whole block of data
-  def putType       = UInt("b010") // Put a single beat of data
+  def putType         = UInt("b010") // Put a single beat of data
-  def putBlockType  = UInt("b011") // Put a whole block of data
+  def putBlockType    = UInt("b011") // Put a whole block of data
-  def putAtomicType = UInt("b100") // Perform an atomic memory op
+  def putAtomicType   = UInt("b100") // Perform an atomic memory op
-  def prefetchType  = UInt("b101") // Prefetch a whole block of data
+  def getPrefetchType = UInt("b101") // Prefetch a whole block of data
+  def putPrefetchType = UInt("b110") // Prefetch a whole block of data, with intent to write
   def typesWithData = Vec(putType, putBlockType, putAtomicType)
   def typesWithMultibeatData = Vec(putBlockType)
   def typesOnSubBlocks = Vec(putType, getType, putAtomicType)
@@ -332,7 +334,8 @@ object Acquire {
       Acquire.putType       -> Grant.putAckType,
       Acquire.putBlockType  -> Grant.putAckType,
       Acquire.putAtomicType -> Grant.getDataBeatType,
-      Acquire.prefetchType  -> Grant.prefetchAckType))
+      Acquire.getPrefetchType -> Grant.prefetchAckType,
+      Acquire.putPrefetchType -> Grant.prefetchAckType))
   }
 
   def makeUnion(
@@ -348,7 +351,8 @@ object Acquire {
       Acquire.putType       -> Cat(wmask, alloc),
       Acquire.putBlockType  -> Cat(wmask, alloc),
       Acquire.putAtomicType -> Cat(addr_byte, operand_size, opcode, alloc),
-      Acquire.prefetchType  -> Cat(opcode, alloc)))
+      Acquire.getPrefetchType -> Cat(M_XRD, alloc),
+      Acquire.putPrefetchType -> Cat(M_XWR, alloc)))
   }
 
   def fullWriteMask(implicit p: Parameters) = SInt(-1, width = p(TLKey(p(TLId))).writeMaskBits).toUInt
@@ -489,10 +493,9 @@ object GetPrefetch {
        addr_block: UInt)
       (implicit p: Parameters): Acquire = {
     BuiltInAcquireBuilder(
-      a_type = Acquire.prefetchType,
+      a_type = Acquire.getPrefetchType,
       client_xact_id = client_xact_id,
-      addr_block = addr_block,
+      addr_block = addr_block)
-      opcode = M_XRD)
   }
 }
 
@@ -587,10 +590,9 @@ object PutPrefetch {
         addr_block: UInt)
       (implicit p: Parameters): Acquire = {
     BuiltInAcquireBuilder(
-      a_type = Acquire.prefetchType,
+      a_type = Acquire.putPrefetchType,
       client_xact_id = client_xact_id,
-      addr_block = addr_block,
+      addr_block = addr_block)
-      opcode = M_XWR)
   }
 }