riscv/rocket-chip
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rocketchip: TileInterrupts needs a TLCacheEdge (#456)

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Wesley W. Terpstra 2016-11-25 17:02:29 -08:00 committed by GitHub
parent 1e0aca7358
commit 2b80386a9e
1 changed files with 1 additions and 1 deletions
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src/main/scala/coreplex/RocketTiles.scala
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@ -57,7 +57,7 @@ class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule {
val uncached = uncachedOut.bundleOut val uncached = uncachedOut.bundleOut
val slave = slaveNode.map(_.bundleIn) val slave = slaveNode.map(_.bundleIn)
val hartid = UInt(INPUT, p(XLen)) val hartid = UInt(INPUT, p(XLen))
val interrupts = new TileInterrupts().asInput val interrupts = new TileInterrupts()(rocket.coreParams).asInput
val resetVector = UInt(INPUT, p(XLen)) val resetVector = UInt(INPUT, p(XLen))
} }
rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3) rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3)