From 2b80386a9e6aa965acbe2fadbb3e129390972cec Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 25 Nov 2016 17:02:29 -0800 Subject: [PATCH] rocketchip: TileInterrupts needs a TLCacheEdge (#456) --- src/main/scala/coreplex/RocketTiles.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/RocketTiles.scala b/src/main/scala/coreplex/RocketTiles.scala index 78a1097a..def17d2a 100644 --- a/src/main/scala/coreplex/RocketTiles.scala +++ b/src/main/scala/coreplex/RocketTiles.scala @@ -57,7 +57,7 @@ class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { val uncached = uncachedOut.bundleOut val slave = slaveNode.map(_.bundleIn) val hartid = UInt(INPUT, p(XLen)) - val interrupts = new TileInterrupts().asInput + val interrupts = new TileInterrupts()(rocket.coreParams).asInput val resetVector = UInt(INPUT, p(XLen)) } rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3)