first commit

groundtest/build.sbt

@@ -0,0 +1,10 @@
+organization := "edu.berkeley.cs"
+
+version := "1.2"
+
+name := "groundtest"
+
+scalaVersion := "2.11.6"
+
+libraryDependencies ++= (Seq("chisel", "hardfloat", "uncore", "junctions", "rocket").map {
+  dep: String => sys.props.get(dep + "Version") map { "edu.berkeley.cs" %% dep % _ }}).flatten

groundtest/src/main/scala/generator.scala

@@ -0,0 +1,93 @@
+package groundtest
+
+import Chisel._
+import uncore._
+import junctions._
+import scala.util.Random
+import cde.{Parameters, Field}
+
+case object BuildGenerator extends Field[(Int, Random, Parameters) => TileLinkGenerator]
+case object NGeneratorsPerTile extends Field[Int]
+case object NGeneratorTiles extends Field[Int]
+
+trait HasGeneratorParams {
+  implicit val p: Parameters
+  val nGensPerTile = p(NGeneratorsPerTile)
+  val nGenTiles = p(NGeneratorTiles)
+  val nGens = nGensPerTile * nGenTiles
+}
+
+abstract class TileLinkGenerator(rnd: Random)
+    (implicit p: Parameters) extends TLModule()(p) with HasGeneratorParams {
+  val io = new Bundle {
+    val tl = new ClientTileLinkIO
+    val finished = Bool(OUTPUT)
+  }
+}
+
+class UncachedTileLinkGenerator(id: Int, rnd: Random)
+    (implicit p: Parameters) extends TileLinkGenerator(rnd)(p) {
+
+  private val tlBlockOffset = tlBeatAddrBits + tlByteAddrBits
+  private val maxAddress = (p(MMIOBase) >> tlBlockOffset).toInt
+  private val totalRequests = maxAddress / nGens
+
+  def rndDataBeat(): UInt = { UInt(BigInt(tlDataBits, rnd), tlDataBits) }
+
+  val (s_start :: s_put :: s_get :: s_finished :: Nil) = Enum(Bits(), 4)
+  val state = Reg(init = s_start)
+
+  val (acq_beat, acq_done) = Counter(io.tl.acquire.fire() && state === s_put, tlDataBeats)
+  val (gnt_beat, gnt_done) = Counter(io.tl.grant.fire() && state === s_get, tlDataBeats)
+  val (req_cnt, req_wrap) = Counter(gnt_done && state === s_get, totalRequests)
+
+  val addr_block = Cat(req_cnt, UInt(id, log2Up(nGens)))
+
+  val sending = Reg(init = Bool(false))
+
+  when (state === s_start) {
+    sending := Bool(true)
+    state := s_put
+  }
+
+  when (state === s_put) {
+    when (acq_done) { sending := Bool(false) }
+    when (io.tl.grant.fire()) { sending := Bool(true); state := s_get }
+  }
+
+  when (state === s_get) {
+    when (io.tl.acquire.fire()) { sending := Bool(false) }
+    when (gnt_done) {
+      sending := Bool(true)
+      state := Mux(req_wrap, s_finished, s_put)
+    }
+  }
+
+  io.finished := (state === s_finished)
+
+  val full_addr = Cat(addr_block, acq_beat, UInt(0, tlByteAddrBits))
+  val put_data = Cat(UInt(id, log2Up(nGens)), req_cnt, full_addr)
+
+  val put_acquire = PutBlock(
+    client_xact_id = UInt(0),
+    addr_block = addr_block,
+    addr_beat = acq_beat,
+    data = put_data)
+
+  val get_acquire = GetBlock(
+    client_xact_id = UInt(0),
+    addr_block = addr_block)
+
+  io.tl.acquire.valid := sending
+  io.tl.acquire.bits := Mux(state === s_put, put_acquire, get_acquire)
+  io.tl.grant.ready := !sending
+
+  assert(!io.tl.grant.valid || state != s_get ||
+    io.tl.grant.bits.data === put_data,
+    "Get received incorrect data")
+
+  io.tl.release.valid := Bool(false)
+  io.tl.probe.ready := Bool(false)
+
+  assert(!io.tl.probe.valid, "Uncached generator cannot accept probes")
+}

groundtest/src/main/scala/tile.scala

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+package groundtest
+
+import Chisel._
+import rocket._
+import uncore._
+import scala.util.Random
+import cde.Parameters
+
+class GeneratorTile(id: Int, rnd: Random, resetSignal: Bool)
+                   (implicit val p: Parameters) extends Tile(resetSignal)(p)
+                   with HasGeneratorParams {
+  val gen_finished = Wire(Vec(nGensPerTile, Bool()))
+
+  val arb = Module(new ClientTileLinkIOArbiter(nGensPerTile))
+
+  for (i <- 0 until nGensPerTile) {
+    val genid = id * nGensPerTile + i
+    val generator = p(BuildGenerator)(genid, rnd, p)
+    arb.io.in(i) <> generator.io.tl
+    gen_finished(i) := generator.io.finished
+  }
+
+  io.cached(0) <> arb.io.out
+  io.uncached(0).acquire.valid := Bool(false)
+  io.uncached(0).grant.ready := Bool(false)
+
+  val all_done = gen_finished.reduce(_ && _)
+
+  val csr_resp_valid = Reg(Bool()) // Don't reset
+  val csr_resp_data = Reg(io.host.csr.resp.bits)
+
+  io.host.csr.req.ready := Bool(true)
+  io.host.csr.resp.valid := csr_resp_valid
+  io.host.csr.resp.bits := csr_resp_data
+
+  when (io.host.csr.req.fire()) {
+    val req = io.host.csr.req.bits
+    csr_resp_valid := Bool(true)
+    csr_resp_data := Mux(req.addr === UInt(CSRs.mtohost), all_done, req.data)
+  }
+
+  when (io.host.csr.resp.fire()) {
+    csr_resp_valid := Bool(false)
+  }
+}