replace ioDCache with ioMem
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1d41a41afa
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2b1c07c723
@ -20,12 +20,11 @@ class ioMem() extends Bundle
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class ioMemArbiter(n: Int) extends Bundle() {
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val mem = new ioMem();
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val requestor = Vec(n) { new ioDCache() }
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val requestor = Vec(n) { new ioMem().flip() }
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}
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class rocketMemArbiter(n: Int) extends Component {
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val io = new ioMemArbiter(n);
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require(io.mem.req_tag.getWidth >= log2up(n) + io.requestor(0).req_tag.getWidth)
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var req_val = Bool(false)
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var req_rdy = io.mem.req_rdy
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@ -216,7 +216,7 @@ class CoherenceHubNoDir extends CoherenceHub {
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }
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val mem = new ioDCache().flip
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val mem = new ioMem
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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@ -183,8 +183,8 @@ object Constants
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val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
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val TILE_ID_BITS = 1
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val TILE_XACT_ID_BITS = 1 // log2(NMSHR)
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val GLOBAL_XACT_ID_BITS = IDX_BITS // if one active xact per set
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val NGLOBAL_XACTS = 1 << IDX_BITS
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val GLOBAL_XACT_ID_BITS = 4
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val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS
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val TTYPE_BITS = 2
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val X_READ_SHARED = UFix(0, TTYPE_BITS)
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@ -198,11 +198,10 @@ object Constants
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val P_COPY = UFix(2, PTYPE_BITS)
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// external memory interface
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val IMEM_TAG_BITS = 1;
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val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;
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val MEM_TAG_BITS = 2 + max(IMEM_TAG_BITS, DMEM_TAG_BITS);
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val MEM_DATA_BITS = 128;
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val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS;
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val MEM_TAG_BITS = 4
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val MEM_DATA_BITS = 128
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val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS
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require(MEM_TAG_BITS >= max(log2up(NMSHR)+1, GLOBAL_XACT_ID_BITS))
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val DTLB_ENTRIES = 8;
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val ITLB_ENTRIES = 8;
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@ -26,7 +26,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component
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val io = new Bundle {
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val host = new ioHost(w)
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val cpu = Vec(ncores) { new ioHTIF().flip() }
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val mem = new ioDCache().flip()
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val mem = new ioMem
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}
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val short_request_bits = 64
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@ -20,7 +20,7 @@ class ioImem(view: List[String] = null) extends Bundle (view)
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class ioRocketICache extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioDCache().flip()
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val mem = new ioMem
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}
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// basic direct mapped instruction cache
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@ -6,8 +6,8 @@ import Constants._;
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import scala.math._;
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class ioIPrefetcher extends Bundle() {
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val icache = new ioDCache();
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val mem = new ioDCache().flip()
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val icache = new ioMem().flip
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val mem = new ioMem
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val invalidate = Bool(INPUT)
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}
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@ -136,7 +136,7 @@ class DataArrayArrayReq extends Bundle {
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class MemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = DMEM_TAG_BITS)
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val tag = Bits(width = MEM_TAG_BITS)
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}
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class WritebackReq extends Bundle {
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@ -281,7 +281,7 @@ class MSHRFile extends Component {
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val req_way_oh = Bits(NWAYS, INPUT)
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val mem_resp_val = Bool(INPUT)
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val mem_resp_tag = Bits(DMEM_TAG_BITS, INPUT)
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val mem_resp_tag = Bits(MEM_TAG_BITS, INPUT)
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val mem_resp_idx = Bits(IDX_BITS, OUTPUT)
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val mem_resp_way_oh = Bits(NWAYS, OUTPUT)
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@ -671,19 +671,6 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
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val resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT);
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}
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// interface between D$ and next level in memory hierarchy
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class ioDCache(view: List[String] = null) extends Bundle(view) {
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val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
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val req_tag = UFix(DMEM_TAG_BITS, INPUT);
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val req_val = Bool(INPUT);
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val req_rdy = Bool(OUTPUT);
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val req_wdata = Bits(MEM_DATA_BITS, INPUT);
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val req_rw = Bool(INPUT);
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val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
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val resp_tag = Bits(DMEM_TAG_BITS, OUTPUT);
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val resp_val = Bool(OUTPUT);
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}
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abstract class HellaCache extends Component {
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def isHit ( cmd: Bits, state: UFix): Bool
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def isValid (state: UFix): Bool
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@ -698,7 +685,7 @@ abstract class HellaCache extends Component {
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class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
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val io = new Bundle {
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val cpu = new ioDmem()
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val mem = new ioDCache().flip
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val mem = new ioMem
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}
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val lines = 1 << IDX_BITS
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