From 2b1c07c723ed5a4d879c3c60fa910a9bdcb886ee Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 27 Feb 2012 18:36:09 -0800 Subject: [PATCH] replace ioDCache with ioMem --- rocket/src/main/scala/arbiter.scala | 3 +-- rocket/src/main/scala/coherence.scala | 2 +- rocket/src/main/scala/consts.scala | 13 ++++++------- rocket/src/main/scala/htif.scala | 2 +- rocket/src/main/scala/icache.scala | 2 +- rocket/src/main/scala/icache_prefetch.scala | 4 ++-- rocket/src/main/scala/nbdcache.scala | 19 +++---------------- 7 files changed, 15 insertions(+), 30 deletions(-) diff --git a/rocket/src/main/scala/arbiter.scala b/rocket/src/main/scala/arbiter.scala index dcbada4c..50f66a58 100644 --- a/rocket/src/main/scala/arbiter.scala +++ b/rocket/src/main/scala/arbiter.scala @@ -20,12 +20,11 @@ class ioMem() extends Bundle class ioMemArbiter(n: Int) extends Bundle() { val mem = new ioMem(); - val requestor = Vec(n) { new ioDCache() } + val requestor = Vec(n) { new ioMem().flip() } } class rocketMemArbiter(n: Int) extends Component { val io = new ioMemArbiter(n); - require(io.mem.req_tag.getWidth >= log2up(n) + io.requestor(0).req_tag.getWidth) var req_val = Bool(false) var req_rdy = io.mem.req_rdy diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala index 8aff1592..d5a5e414 100644 --- a/rocket/src/main/scala/coherence.scala +++ b/rocket/src/main/scala/coherence.scala @@ -216,7 +216,7 @@ class CoherenceHubNoDir extends CoherenceHub { val io = new Bundle { val tiles = Vec(NTILES) { new ioTileLink() } - val mem = new ioDCache().flip + val mem = new ioMem } val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_)) diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala index 8b55c39f..17294bae 100644 --- a/rocket/src/main/scala/consts.scala +++ b/rocket/src/main/scala/consts.scala @@ -183,8 +183,8 @@ object Constants val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8 val TILE_ID_BITS = 1 val TILE_XACT_ID_BITS = 1 // log2(NMSHR) - val GLOBAL_XACT_ID_BITS = IDX_BITS // if one active xact per set - val NGLOBAL_XACTS = 1 << IDX_BITS + val GLOBAL_XACT_ID_BITS = 4 + val NGLOBAL_XACTS = 1 << GLOBAL_XACT_ID_BITS val TTYPE_BITS = 2 val X_READ_SHARED = UFix(0, TTYPE_BITS) @@ -198,11 +198,10 @@ object Constants val P_COPY = UFix(2, PTYPE_BITS) // external memory interface - val IMEM_TAG_BITS = 1; - val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt; - val MEM_TAG_BITS = 2 + max(IMEM_TAG_BITS, DMEM_TAG_BITS); - val MEM_DATA_BITS = 128; - val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS; + val MEM_TAG_BITS = 4 + val MEM_DATA_BITS = 128 + val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS + require(MEM_TAG_BITS >= max(log2up(NMSHR)+1, GLOBAL_XACT_ID_BITS)) val DTLB_ENTRIES = 8; val ITLB_ENTRIES = 8; diff --git a/rocket/src/main/scala/htif.scala b/rocket/src/main/scala/htif.scala index d229667e..77d189eb 100644 --- a/rocket/src/main/scala/htif.scala +++ b/rocket/src/main/scala/htif.scala @@ -26,7 +26,7 @@ class rocketHTIF(w: Int, ncores: Int) extends Component val io = new Bundle { val host = new ioHost(w) val cpu = Vec(ncores) { new ioHTIF().flip() } - val mem = new ioDCache().flip() + val mem = new ioMem } val short_request_bits = 64 diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 0c8d758b..09cbb156 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -20,7 +20,7 @@ class ioImem(view: List[String] = null) extends Bundle (view) class ioRocketICache extends Bundle() { val cpu = new ioImem(); - val mem = new ioDCache().flip() + val mem = new ioMem } // basic direct mapped instruction cache diff --git a/rocket/src/main/scala/icache_prefetch.scala b/rocket/src/main/scala/icache_prefetch.scala index b9144cd7..104257e0 100644 --- a/rocket/src/main/scala/icache_prefetch.scala +++ b/rocket/src/main/scala/icache_prefetch.scala @@ -6,8 +6,8 @@ import Constants._; import scala.math._; class ioIPrefetcher extends Bundle() { - val icache = new ioDCache(); - val mem = new ioDCache().flip() + val icache = new ioMem().flip + val mem = new ioMem val invalidate = Bool(INPUT) } diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 2147cd21..89a4e5c6 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -136,7 +136,7 @@ class DataArrayArrayReq extends Bundle { class MemReq extends Bundle { val rw = Bool() val addr = UFix(width = PADDR_BITS-OFFSET_BITS) - val tag = Bits(width = DMEM_TAG_BITS) + val tag = Bits(width = MEM_TAG_BITS) } class WritebackReq extends Bundle { @@ -281,7 +281,7 @@ class MSHRFile extends Component { val req_way_oh = Bits(NWAYS, INPUT) val mem_resp_val = Bool(INPUT) - val mem_resp_tag = Bits(DMEM_TAG_BITS, INPUT) + val mem_resp_tag = Bits(MEM_TAG_BITS, INPUT) val mem_resp_idx = Bits(IDX_BITS, OUTPUT) val mem_resp_way_oh = Bits(NWAYS, OUTPUT) @@ -670,19 +670,6 @@ class ioDmem(view: List[String] = null) extends Bundle(view) { val resp_data_subword = Bits(64, OUTPUT); val resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT); } - -// interface between D$ and next level in memory hierarchy -class ioDCache(view: List[String] = null) extends Bundle(view) { - val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT); - val req_tag = UFix(DMEM_TAG_BITS, INPUT); - val req_val = Bool(INPUT); - val req_rdy = Bool(OUTPUT); - val req_wdata = Bits(MEM_DATA_BITS, INPUT); - val req_rw = Bool(INPUT); - val resp_data = Bits(MEM_DATA_BITS, OUTPUT); - val resp_tag = Bits(DMEM_TAG_BITS, OUTPUT); - val resp_val = Bool(OUTPUT); -} abstract class HellaCache extends Component { def isHit ( cmd: Bits, state: UFix): Bool @@ -698,7 +685,7 @@ abstract class HellaCache extends Component { class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence { val io = new Bundle { val cpu = new ioDmem() - val mem = new ioDCache().flip + val mem = new ioMem } val lines = 1 << IDX_BITS