tilelink: make bus xbar protected so it can be suggestNamed
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@ -44,6 +44,8 @@ case object MemoryBusParams extends Field[MemoryBusParams]
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/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
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class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) {
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xbar.suggestName("MemoryBus")
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def fromCoherenceManager: TLInwardNode = inwardBufNode
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def toDRAMController: TLOutwardNode = outwardBufNode
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def toVariableWidthSlave: TLOutwardNode = outwardFragNode
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@ -22,6 +22,8 @@ case class PeripheryBusParams(
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case object PeripheryBusParams extends Field[PeripheryBusParams]
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class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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xbar.suggestName("PeripheryBus")
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def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
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TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
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}
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@ -18,6 +18,8 @@ case class SystemBusParams(
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case object SystemBusParams extends Field[SystemBusParams]
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class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
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xbar.suggestName("SystemBus")
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private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
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inwardNode :=* master_splitter.node
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def busView = master_splitter.node.edgesIn.head
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@ -30,7 +30,7 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
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private val delayProb = p(TLBusDelayProbability)
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private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None
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private val xbar = LazyModule(new TLXbar)
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protected val xbar = LazyModule(new TLXbar)
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private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
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private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
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private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))
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