From 2910d6fa2aa96c046a7db640deaa05002842cd0c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Mon, 7 Aug 2017 17:30:24 -0700 Subject: [PATCH] tilelink: make bus xbar protected so it can be suggestNamed --- src/main/scala/coreplex/MemoryBus.scala | 2 ++ src/main/scala/coreplex/PeripheryBus.scala | 2 ++ src/main/scala/coreplex/SystemBus.scala | 2 ++ src/main/scala/tilelink/Bus.scala | 2 +- 4 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/main/scala/coreplex/MemoryBus.scala b/src/main/scala/coreplex/MemoryBus.scala index d78cddee..d71507ba 100644 --- a/src/main/scala/coreplex/MemoryBus.scala +++ b/src/main/scala/coreplex/MemoryBus.scala @@ -44,6 +44,8 @@ case object MemoryBusParams extends Field[MemoryBusParams] /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */ class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) { + xbar.suggestName("MemoryBus") + def fromCoherenceManager: TLInwardNode = inwardBufNode def toDRAMController: TLOutwardNode = outwardBufNode def toVariableWidthSlave: TLOutwardNode = outwardFragNode diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala index 42352afa..02d098c2 100644 --- a/src/main/scala/coreplex/PeripheryBus.scala +++ b/src/main/scala/coreplex/PeripheryBus.scala @@ -22,6 +22,8 @@ case class PeripheryBusParams( case object PeripheryBusParams extends Field[PeripheryBusParams] class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) { + xbar.suggestName("PeripheryBus") + def toFixedWidthSingleBeatSlave(widthBytes: Int) = { TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode) } diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala index 9fe8a56b..501bad37 100644 --- a/src/main/scala/coreplex/SystemBus.scala +++ b/src/main/scala/coreplex/SystemBus.scala @@ -18,6 +18,8 @@ case class SystemBusParams( case object SystemBusParams extends Field[SystemBusParams] class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) { + xbar.suggestName("SystemBus") + private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks inwardNode :=* master_splitter.node def busView = master_splitter.node.edgesIn.head diff --git a/src/main/scala/tilelink/Bus.scala b/src/main/scala/tilelink/Bus.scala index d3c143ae..e2a63cfb 100644 --- a/src/main/scala/tilelink/Bus.scala +++ b/src/main/scala/tilelink/Bus.scala @@ -30,7 +30,7 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends private val delayProb = p(TLBusDelayProbability) private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None - private val xbar = LazyModule(new TLXbar) + protected val xbar = LazyModule(new TLXbar) private val master_buffer = LazyModule(new TLBuffer(masterBuffering)) private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering)) private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))