riscv/rocket-chip
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tilelink: make bus xbar protected so it can be suggestNamed

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Henry Cook
2017-08-07 17:30:24 -07:00
parent c457c9cb9f
commit 2910d6fa2a
4 changed files with 7 additions and 1 deletions
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2
src/main/scala/coreplex/MemoryBus.scala
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@@ -44,6 +44,8 @@ case object MemoryBusParams extends Field[MemoryBusParams]
/** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */ /** Wrapper for creating TL nodes from a bus connected to the back of each mem channel */
class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) { class MemoryBus(params: MemoryBusParams)(implicit p: Parameters) extends TLBusWrapper(params)(p) {
xbar.suggestName("MemoryBus")
def fromCoherenceManager: TLInwardNode = inwardBufNode def fromCoherenceManager: TLInwardNode = inwardBufNode
def toDRAMController: TLOutwardNode = outwardBufNode def toDRAMController: TLOutwardNode = outwardBufNode
def toVariableWidthSlave: TLOutwardNode = outwardFragNode def toVariableWidthSlave: TLOutwardNode = outwardFragNode

2
src/main/scala/coreplex/PeripheryBus.scala
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@@ -22,6 +22,8 @@ case class PeripheryBusParams(
case object PeripheryBusParams extends Field[PeripheryBusParams] case object PeripheryBusParams extends Field[PeripheryBusParams]
class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) { class PeripheryBus(params: PeripheryBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
xbar.suggestName("PeripheryBus")
def toFixedWidthSingleBeatSlave(widthBytes: Int) = { def toFixedWidthSingleBeatSlave(widthBytes: Int) = {
TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode) TLFragmenter(widthBytes, params.blockBytes)(outwardWWNode)
} }

2
src/main/scala/coreplex/SystemBus.scala
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@@ -18,6 +18,8 @@ case class SystemBusParams(
case object SystemBusParams extends Field[SystemBusParams] case object SystemBusParams extends Field[SystemBusParams]
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) { class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
xbar.suggestName("SystemBus")
private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
inwardNode :=* master_splitter.node inwardNode :=* master_splitter.node
def busView = master_splitter.node.edgesIn.head def busView = master_splitter.node.edgesIn.head

2
src/main/scala/tilelink/Bus.scala
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@@ -30,7 +30,7 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
private val delayProb = p(TLBusDelayProbability) private val delayProb = p(TLBusDelayProbability)
private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None
private val xbar = LazyModule(new TLXbar) protected val xbar = LazyModule(new TLXbar)
private val master_buffer = LazyModule(new TLBuffer(masterBuffering)) private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering)) private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes)) private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))