riscv/rocket-chip
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tilelink: make bus xbar protected so it can be suggestNamed

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Henry Cook committed 2017-08-07 17:30:24 -07:00
1 parent c457c9cb9f
commit 2910d6fa2a
4 files changed
+7 -1
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src/main/scala/tilelink/Bus.scala
+1 -1
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@@ -30,7 +30,7 @@ abstract class TLBusWrapper(params: TLBusParams)(implicit p: Parameters) extends
private val delayProb = p(TLBusDelayProbability)
private val delayer = if (delayProb > 0.0) Some(LazyModule(new TLDelayer(delayProb))) else None
private val xbar = LazyModule(new TLXbar)
protected val xbar = LazyModule(new TLXbar)
private val master_buffer = LazyModule(new TLBuffer(masterBuffering))
private val slave_buffer = LazyModule(new TLBuffer(slaveBuffering))
private val slave_frag = LazyModule(new TLFragmenter(beatBytes, blockBytes))