riscv/rocket-chip
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tilelink: make bus xbar protected so it can be suggestNamed

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Henry Cook
2017-08-07 17:30:24 -07:00
parent c457c9cb9f
commit 2910d6fa2a
4 changed files with 7 additions and 1 deletions
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2
src/main/scala/coreplex/SystemBus.scala
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@ -18,6 +18,8 @@ case class SystemBusParams(
case object SystemBusParams extends Field[SystemBusParams]
class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWrapper(params) {
xbar.suggestName("SystemBus")
private val master_splitter = LazyModule(new TLSplitter) // Allows cycle-free connection to external networks
inwardNode :=* master_splitter.node
def busView = master_splitter.node.edgesIn.head