riscv/rocket-chip
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don't JALR to speculatively-bypassed addresses

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Technically not necessary, but probably improves performance.
This commit is contained in:
Andrew Waterman
2013-05-21 16:53:47 -07:00
parent dcde377303
commit 28f914c3f2
1 changed files with 7 additions and 5 deletions
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12
rocket/src/main/scala/ctrl.scala
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@@ -516,12 +516,14 @@ class Control(implicit conf: RocketConfiguration) extends Component
// replay inst in ex stage
val wb_dcache_miss = wb_reg_mem_val && !io.dmem.resp.valid
val replay_ex = wb_dcache_miss && ex_reg_load_use || mem_reg_flush_inst ||
ex_reg_mem_val && !io.dmem.req.ready ||
ex_reg_div_mul_val && !io.dpath.div_mul_rdy ||
mem_reg_replay_next
val replay_ex_structural = ex_reg_mem_val && !io.dmem.req.ready ||
ex_reg_div_mul_val && !io.dpath.div_mul_rdy
val replay_ex_other = wb_dcache_miss && ex_reg_load_use || mem_reg_replay_next
val replay_ex = replay_ex_structural || replay_ex_other
ctrl_killx := take_pc_wb || replay_ex
val take_pc_ex = !Mux(ex_reg_jalr, ex_reg_btb_hit && io.dpath.jalr_eq, ex_reg_btb_hit === io.dpath.ex_br_taken)
val take_pc_ex = !Mux(ex_reg_jalr,
ex_reg_btb_hit && io.dpath.jalr_eq && !replay_ex_other,
ex_reg_btb_hit === io.dpath.ex_br_taken)
// detect 2-cycle load-use delay for LB/LH/SC
val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || AVec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type)