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BankedL2Config: use the same LazyModule for all L2 banks

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This makes it much easier for banked coherence managers to support
cross-bank functionality, like a common control port, for example.
This commit is contained in:
Wesley W. Terpstra 2017-01-30 14:02:59 -08:00
parent b567a2a356
commit 280af9684b
3 changed files with 11 additions and 8 deletions
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7
src/main/scala/coreplex/BaseCoreplex.scala
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@ -22,15 +22,16 @@ case class BroadcastConfig(
case object BroadcastConfig extends Field[BroadcastConfig] case object BroadcastConfig extends Field[BroadcastConfig]
/** L2 memory subsystem configuration */ /** L2 memory subsystem configuration */
case class BankedL2Geometry(bank: Int, banks: Int, channel: Int, channels: Int)
case class BankedL2Config( case class BankedL2Config(
nMemoryChannels: Int = 1, nMemoryChannels: Int = 1,
nBanksPerChannel: Int = 1, nBanksPerChannel: Int = 1,
coherenceManager: (Parameters, CoreplexNetwork, BankedL2Geometry) => (TLInwardNode, TLOutwardNode) = { case (q, _, _) => coherenceManager: (Parameters, CoreplexNetwork) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
implicit val p = q implicit val p = q
val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig) val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless)) val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
(bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node)) val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
ww.node :*= bh.node
(bh.node, ww.node)
}) { }) {
val nBanks = nMemoryChannels*nBanksPerChannel val nBanks = nMemoryChannels*nBanksPerChannel
} }

6
src/main/scala/coreplex/Configs.scala
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@ -144,10 +144,12 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
* DO NOT use this configuration. * DO NOT use this configuration.
*/ */
class WithStatelessBridge extends Config((site, here, up) => { class WithStatelessBridge extends Config((site, here, up) => {
case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _, _) => case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _) =>
implicit val p = q implicit val p = q
val cork = LazyModule(new TLCacheCork(unsafe = true)) val cork = LazyModule(new TLCacheCork(unsafe = true))
(cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node)) val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
ww.node :*= cork.node
(cork.node, ww.node)
}) })
case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0) case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
}) })

6
src/main/scala/coreplex/CoreplexNetwork.scala
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@ -77,13 +77,13 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
val mem = TLOutputNode() val mem = TLOutputNode()
for (channel <- 0 until l2Config.nMemoryChannels) { for (channel <- 0 until l2Config.nMemoryChannels) {
val bankBar = LazyModule(new TLXbar) val bankBar = LazyModule(new TLXbar)
val (in, out) = l2Config.coherenceManager(p, this)
in :*= l1tol2.node
mem := bankBar.node mem := bankBar.node
val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes) val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
for (bank <- 0 until l2Config.nBanksPerChannel) { for (bank <- 0 until l2Config.nBanksPerChannel) {
val geometry = BankedL2Geometry(bank, l2Config.nBanksPerChannel, channel, l2Config.nMemoryChannels)
val (in, out) = l2Config.coherenceManager(p, this, geometry)
in := l1tol2.node
bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out) bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out)
} }
} }