diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index 18d25d80..2906cfbd 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -22,15 +22,16 @@ case class BroadcastConfig(
 case object BroadcastConfig extends Field[BroadcastConfig]
 
 /** L2 memory subsystem configuration */
-case class BankedL2Geometry(bank: Int, banks: Int, channel: Int, channels: Int)
 case class BankedL2Config(
   nMemoryChannels:  Int = 1,
   nBanksPerChannel: Int = 1,
-  coherenceManager: (Parameters, CoreplexNetwork, BankedL2Geometry) => (TLInwardNode, TLOutwardNode) = { case (q, _, _) =>
+  coherenceManager: (Parameters, CoreplexNetwork) => (TLInwardNode, TLOutwardNode) = { case (q, _) =>
     implicit val p = q
     val BroadcastConfig(nTrackers, bufferless) = p(BroadcastConfig)
     val bh = LazyModule(new TLBroadcast(p(CacheBlockBytes), nTrackers, bufferless))
-    (bh.node, TLWidthWidget(p(L1toL2Config).beatBytes)(bh.node))
+    val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
+    ww.node :*= bh.node
+    (bh.node, ww.node)
   }) {
   val nBanks = nMemoryChannels*nBanksPerChannel
 }
diff --git a/src/main/scala/coreplex/Configs.scala b/src/main/scala/coreplex/Configs.scala
index 6a5ed0fe..1c7f9b62 100644
--- a/src/main/scala/coreplex/Configs.scala
+++ b/src/main/scala/coreplex/Configs.scala
@@ -144,10 +144,12 @@ class WithBufferlessBroadcastHub extends Config((site, here, up) => {
  * DO NOT use this configuration.
  */
 class WithStatelessBridge extends Config((site, here, up) => {
-  case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _, _) =>
+  case BankedL2Config => up(BankedL2Config, site).copy(coherenceManager = { case (q, _) =>
     implicit val p = q
     val cork = LazyModule(new TLCacheCork(unsafe = true))
-    (cork.node, TLWidthWidget(p(L1toL2Config).beatBytes)(cork.node))
+    val ww = LazyModule(new TLWidthWidget(p(L1toL2Config).beatBytes))
+    ww.node :*= cork.node
+    (cork.node, ww.node)
   })
   case DCacheKey => up(DCacheKey, site).copy(nMSHRs = 0)
 })
diff --git a/src/main/scala/coreplex/CoreplexNetwork.scala b/src/main/scala/coreplex/CoreplexNetwork.scala
index 2233cad2..9402548b 100644
--- a/src/main/scala/coreplex/CoreplexNetwork.scala
+++ b/src/main/scala/coreplex/CoreplexNetwork.scala
@@ -77,13 +77,13 @@ trait BankedL2CoherenceManagers extends CoreplexNetwork {
   val mem = TLOutputNode()
   for (channel <- 0 until l2Config.nMemoryChannels) {
     val bankBar = LazyModule(new TLXbar)
+    val (in, out) = l2Config.coherenceManager(p, this)
 
+    in :*= l1tol2.node
     mem := bankBar.node
+
     val mask = ~BigInt((l2Config.nBanksPerChannel-1) * l1tol2_lineBytes)
     for (bank <- 0 until l2Config.nBanksPerChannel) {
-      val geometry = BankedL2Geometry(bank, l2Config.nBanksPerChannel, channel, l2Config.nMemoryChannels)
-      val (in, out) = l2Config.coherenceManager(p, this, geometry)
-      in := l1tol2.node
       bankBar.node := TLFilter(AddressSet(bank * l1tol2_lineBytes, mask))(out)
     }
   }