riscv/rocket-chip
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tie off invalidate_lr in RoCC

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This commit is contained in:
Howard Mao 2016-08-31 09:44:32 -07:00
parent bb578494d8
commit 27c674972c
1 changed files with 1 additions and 0 deletions
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src/main/scala/rocket/rocc.scala
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@ -58,6 +58,7 @@ class RoCCInterface(implicit p: Parameters) extends CoreBundle()(p) {
abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) { abstract class RoCC(implicit p: Parameters) extends CoreModule()(p) {
val io = new RoCCInterface val io = new RoCCInterface
io.mem.req.bits.phys := Bool(true) // don't perform address translation io.mem.req.bits.phys := Bool(true) // don't perform address translation
io.mem.invalidate_lr := Bool(false) // don't mess with LR/SC
} }
class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) { class AccumulatorExample(n: Int = 4)(implicit p: Parameters) extends RoCC()(p) {