riscv/rocket-chip
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add CONFIG to the name of simulator executable

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This commit is contained in:
Yunsup Lee
2014-09-11 22:11:58 -07:00
parent c98afa1fea
commit 275b72368b
9 changed files with 54 additions and 49 deletions
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10
vsim/Makefrag
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@ -5,9 +5,9 @@
# Verilog sources
sim_vsrcs = \
$(generated_dir)/$(MODEL).v \
$(generated_dir)/consts.vh \
$(generated_dir)/memdessertMemDessert.v \
$(generated_dir)/$(MODEL).$(CONFIG).v \
$(generated_dir)/consts.$(CONFIG).vh \
$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
$(base_dir)/vsrc/rocketTestHarness.v \
$(base_dir)/vsrc/backup_mem.v \
@ -50,12 +50,12 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
# Build the simulator
#--------------------------------------------------------------------
simv = $(sim_dir)/simv
simv = $(sim_dir)/simv-$(CONFIG)
$(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
cd $(sim_dir) && \
$(VCS) $(VCS_OPTS) -o $(simv) \
simv_debug = $(sim_dir)/simv-debug
simv_debug = $(sim_dir)/simv-$(CONFIG)-debug
$(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
cd $(sim_dir) && \
$(VCS) $(VCS_OPTS) -o $(simv_debug) \