diff --git a/Makefrag b/Makefrag
index 1cac0ceb..a6bd06e7 100644
--- a/Makefrag
+++ b/Makefrag
@@ -27,20 +27,20 @@ timeout_cycles = 100000000
 # Verilog Generation
 #--------------------------------------------------------------------
 
-$(generated_dir)/$(MODEL).v: $(chisel_srcs)
+$(generated_dir)/$(MODEL).$(CONFIG).v: $(chisel_srcs)
 	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate $(MODEL) --backend $(BACKEND) --targetDir $(generated_dir) --noInlineMem --configInstance rocketchip.$(CONFIG) --configDump"
 	cd $(generated_dir) && \
-	if [ -a $(MODEL).conf ]; then \
-	  $(mem_gen) $(generated_dir)/$(MODEL).conf >> $(generated_dir)/$(MODEL).v; \
+	if [ -a $(MODEL).$(CONFIG).conf ]; then \
+	  $(mem_gen) $(generated_dir)/$(MODEL).$(CONFIG).conf >> $(generated_dir)/$(MODEL).$(CONFIG).v; \
 	fi
 
-$(generated_dir)/consts.vh: $(generated_dir)/rocketchip.$(CONFIG).prm
+$(generated_dir)/consts.$(CONFIG).vh: $(generated_dir)/$(MODEL).$(CONFIG).v
 	echo "\`ifndef CONST_VH" > $@
 	echo "\`define CONST_VH" >> $@
-	sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $< >> $@
+	sed -r 's/\(([A-Za-z0-9_]+),([A-Za-z0-9_]+)\)/`define \1 \2/' $(patsubst %.v,%.prm,$<) >> $@
 	echo "\`endif // CONST_VH" >> $@
 
-$(generated_dir)/memdessertMemDessert.v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
+$(generated_dir)/memdessertMemDessert.$(CONFIG).v: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
 	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "project rocketchip" "elaborate MemDessert --backend v --targetDir $(generated_dir) --moduleNamePrefix memdessert --configInstance rocketchip.$(CONFIG)"
 
 #--------------------------------------------------------------------
diff --git a/chisel b/chisel
index 94650dae..b2879323 160000
--- a/chisel
+++ b/chisel
@@ -1 +1 @@
-Subproject commit 94650dae31260a2d48ef02d99389b1f392ddee43
+Subproject commit b28793236e2a6bc73d88063932c84235a0ba6a18
diff --git a/csrc/emulator.cc b/csrc/emulator.cc
index 167a88ae..7e51cc96 100644
--- a/csrc/emulator.cc
+++ b/csrc/emulator.cc
@@ -2,7 +2,6 @@
 #include "emulator.h"
 #include "mm.h"
 #include "mm_dramsim2.h"
-#include "Top.h" // chisel-generated code...
 #include <fcntl.h>
 #include <signal.h>
 #include <stdio.h>
diff --git a/emulator/.gitignore b/emulator/.gitignore
index 9b61a13d..85a56464 100644
--- a/emulator/.gitignore
+++ b/emulator/.gitignore
@@ -3,9 +3,8 @@
 *.a
 *.log
 output/
-emulator
+emulator-*
 generated-src
-emulator-debug
 generated-src-debug
 kernel
 kernel.hex
diff --git a/emulator/Makefile b/emulator/Makefile
index 319996bb..f03e5c8e 100644
--- a/emulator/Makefile
+++ b/emulator/Makefile
@@ -1,11 +1,12 @@
-all: emulator
-
 base_dir = $(abspath ..)
 sim_dir = .
 output_dir = $(sim_dir)/output
 PROJECT = rocketchip
 CONFIG = DefaultCPPConfig
 
+all: emulator-$(CONFIG)
+debug: emulator-$(CONFIG)-debug
+
 include $(base_dir)/Makefrag
 
 CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include
@@ -15,46 +16,46 @@ CXXFLAGS := $(CXXFLAGS) -I$(base_dir)/csrc -I$(base_dir)/dramsim2
 
 LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -Wl,-rpath,$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
 
-OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
-DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
+OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL).$(CONFIG))
+DEBUG_OBJS := $(addsuffix .debug.o,$(CXXSRCS) $(MODEL).$(CONFIG))
 
 CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --configInstance $(PROJECT).$(CONFIG) --targetDir emulator/generated-src
 CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
 
-generated-src/$(MODEL).h: $(chisel_srcs)
+generated-src/$(MODEL).$(CONFIG).h: $(chisel_srcs)
 	cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS)"
 
-generated-src-debug/$(MODEL).h: $(chisel_srcs)
+generated-src-debug/$(MODEL).$(CONFIG).h: $(chisel_srcs)
 	cd $(base_dir) && $(SBT) "project $(PROJECT)" "elaborate $(CHISEL_ARGS_DEBUG)"
 
-$(MODEL).o: %.o: generated-src/%.h
-	$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp))
-	$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL)-*.cpp)) -o $@
+$(MODEL).$(CONFIG).o: %.o: generated-src/%.h
+	$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL).$(CONFIG)-*.cpp))
+	$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src/$(MODEL).$(CONFIG)-*.cpp)) -o $@
 
-$(MODEL)-debug.o: %-debug.o: generated-src-debug/%.h
-	$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp))
-	$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL)-*.cpp)) -o $@
+$(MODEL).$(CONFIG).debug.o: %.debug.o: generated-src-debug/%.h
+	$(MAKE) -j $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL).$(CONFIG)-*.cpp))
+	$(LD) -r $(patsubst %.cpp,%.o,$(shell ls generated-src-debug/$(MODEL).$(CONFIG)-*.cpp)) -o $@
 
-$(wildcard generated-src/*.o): %.o: %.cpp generated-src/$(MODEL).h
+$(wildcard generated-src/*.o): %.o: %.cpp generated-src/$(MODEL).$(CONFIG).h
 	$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
 
-$(wildcard generated-src-debug/*.o): %.o: %.cpp generated-src-debug/$(MODEL).h
+$(wildcard generated-src-debug/*.o): %.o: %.cpp generated-src-debug/$(MODEL).$(CONFIG).h
 	$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
 
-$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).h
-	$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
+$(addsuffix .o,$(CXXSRCS)): %.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src/$(MODEL).$(CONFIG).h
+	$(CXX) $(CXXFLAGS) -include generated-src/$(MODEL).$(CONFIG).h -Igenerated-src -c -o $@ $<
 
-$(addsuffix -debug.o,$(CXXSRCS)): %-debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).h
-	$(CXX) $(CXXFLAGS) -Igenerated-src-debug -c -o $@ $<
+$(addsuffix .debug.o,$(CXXSRCS)): %.debug.o: $(base_dir)/csrc/%.cc $(base_dir)/csrc/*.h generated-src-debug/$(MODEL).$(CONFIG).h
+	$(CXX) $(CXXFLAGS) -include generated-src-debug/$(MODEL).$(CONFIG).h -Igenerated-src-debug -c -o $@ $<
 
-emulator: $(OBJS) libdramsim.a
+emulator-$(CONFIG): $(OBJS) libdramsim.a
 	$(CXX) $(CXXFLAGS) -o $@ $(OBJS) $(LDFLAGS)
 
-emulator-debug: $(DEBUG_OBJS) libdramsim.a
+emulator-$(CONFIG)-debug: $(DEBUG_OBJS) libdramsim.a
 	$(CXX) $(CXXFLAGS) -o $@ $(DEBUG_OBJS) $(LDFLAGS)
  
 clean:
-	rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles $(output_dir)
+	rm -rf *.o *.a emulator-* emulator-*-debug generated-src generated-src-debug DVEfiles $(output_dir)
 
 test:
 	cd $(base_dir) && $(SBT) "~make $(CURDIR) run-fast $(CHISEL_ARGS)"
@@ -63,19 +64,19 @@ test:
 # Run assembly tests and benchmarks
 #--------------------------------------------------------------------
 
-$(output_dir)/%.run: $(output_dir)/%.hex emulator
-	./emulator +dramsim +max-cycles=$(timeout_cycles) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
+$(output_dir)/%.run: $(output_dir)/%.hex emulator-$(CONFIG)
+	./emulator-$(CONFIG) +dramsim +max-cycles=$(timeout_cycles) +loadmem=$< none 2> /dev/null 2> $@ && [ $$PIPESTATUS -eq 0 ]
 
-$(output_dir)/%.out: $(output_dir)/%.hex emulator
-	./emulator +dramsim +max-cycles=$(timeout_cycles) +verbose +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
+$(output_dir)/%.out: $(output_dir)/%.hex emulator-$(CONFIG)
+	./emulator-$(CONFIG) +dramsim +max-cycles=$(timeout_cycles) +verbose +loadmem=$< none $(disasm) $@ && [ $$PIPESTATUS -eq 0 ]
 
-$(output_dir)/%.vcd: $(output_dir)/%.hex emulator-debug
-	./emulator-debug +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@ +loadmem=$< none $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
+$(output_dir)/%.vcd: $(output_dir)/%.hex emulator-$(CONFIG)-debug
+	./emulator-$(CONFIG)-debug +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@ +loadmem=$< none $(disasm) $(patsubst %.vcd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
 
-$(output_dir)/%.vpd: $(output_dir)/%.hex emulator-debug
+$(output_dir)/%.vpd: $(output_dir)/%.hex emulator-$(CONFIG)-debug
 	rm -rf $@.vcd && mkfifo $@.vcd
 	vcd2vpd $@.vcd $@ > /dev/null &
-	./emulator-debug +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@.vcd +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
+	./emulator-$(CONFIG)-debug +dramsim +max-cycles=$(timeout_cycles) +verbose -v$@.vcd +loadmem=$< none $(disasm) $(patsubst %.vpd,%.out,$@) && [ $$PIPESTATUS -eq 0 ]
 
 run-asm-tests: $(addprefix $(output_dir)/, $(addsuffix .out, $(asm_p_tests) $(asm_v_tests)))
 	@echo; perl -ne 'print "  [$$1] $$ARGV \t$$2\n" if /\*{3}(.{8})\*{3}(.*)/' $^; echo;
diff --git a/fsim/Makefile b/fsim/Makefile
index da2cc2ac..8b9a317c 100644
--- a/fsim/Makefile
+++ b/fsim/Makefile
@@ -23,6 +23,9 @@ include $(sim_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim
 
 all: $(simv)
+debug: $(simv_debug)
 
 clean:
 	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
+
+.PHONY: default all debug clean
diff --git a/fsim/Makefrag b/fsim/Makefrag
index 7ffc37e5..caf1cabd 100644
--- a/fsim/Makefrag
+++ b/fsim/Makefrag
@@ -6,9 +6,9 @@
 # Verilog sources
 
 sim_vsrcs = \
-	$(generated_dir)/$(MODEL).v \
-	$(generated_dir)/consts.vh \
-	$(generated_dir)/memdessertMemDessert.v \
+	$(generated_dir)/$(MODEL).$(CONFIG).v \
+	$(generated_dir)/consts.$(CONFIG).vh \
+	$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
 	$(base_dir)/vsrc/rocketTestHarness.v \
 	$(base_dir)/vsrc/backup_mem.v \
 
@@ -52,12 +52,12 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
 # Build the simulator
 #--------------------------------------------------------------------
 
-simv = $(sim_dir)/simv
+simv = $(sim_dir)/simv-$(CONFIG)
 $(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
 	cd $(sim_dir) && \
 	$(VCS) $(VCS_OPTS) -o $(simv) \
 
-simv_debug = $(sim_dir)/simv-debug
+simv_debug = $(sim_dir)/simv-$(CONFIG)-debug
 $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
 	cd $(sim_dir) && \
 	$(VCS) $(VCS_OPTS) -o $(simv_debug) \
diff --git a/vsim/Makefile b/vsim/Makefile
index bb94827e..48ca070e 100644
--- a/vsim/Makefile
+++ b/vsim/Makefile
@@ -23,6 +23,9 @@ include $(sim_dir)/Makefrag
 include $(base_dir)/vsim/Makefrag-sim
 
 all: $(simv)
+debug: $(simv_debug)
 
 clean:
 	rm -rf $(junk) simv* csrc *.key DVE* *.h *.a *.daidir $(generated_dir)
+
+.PHONY: default all debug clean
diff --git a/vsim/Makefrag b/vsim/Makefrag
index 3947d3e3..79c9bafb 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -5,9 +5,9 @@
 # Verilog sources
 
 sim_vsrcs = \
-	$(generated_dir)/$(MODEL).v \
-	$(generated_dir)/consts.vh \
-	$(generated_dir)/memdessertMemDessert.v \
+	$(generated_dir)/$(MODEL).$(CONFIG).v \
+	$(generated_dir)/consts.$(CONFIG).vh \
+	$(generated_dir)/memdessertMemDessert.$(CONFIG).v \
 	$(base_dir)/vsrc/rocketTestHarness.v \
 	$(base_dir)/vsrc/backup_mem.v \
 
@@ -50,12 +50,12 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -timescale=1ns/10ps -quiet
 # Build the simulator
 #--------------------------------------------------------------------
 
-simv = $(sim_dir)/simv
+simv = $(sim_dir)/simv-$(CONFIG)
 $(simv) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
 	cd $(sim_dir) && \
 	$(VCS) $(VCS_OPTS) -o $(simv) \
 
-simv_debug = $(sim_dir)/simv-debug
+simv_debug = $(sim_dir)/simv-$(CONFIG)-debug
 $(simv_debug) : $(sim_vsrcs) $(sim_csrcs) $(sim_dir)/libdramsim.a
 	cd $(sim_dir) && \
 	$(VCS) $(VCS_OPTS) -o $(simv_debug) \