riscv/rocket-chip
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Refactored uncore conf

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This commit is contained in:
Henry Cook
2012-12-13 11:45:42 -08:00
parent 78868f6075
commit 261e14f831
3 changed files with 8 additions and 8 deletions
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12
rocket/src/main/scala/htif.scala
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@@ -36,11 +36,11 @@ class ioHTIF(ntiles: Int) extends Bundle
val ipi_rep = (new FIFOIO) { Bool() }.flip val ipi_rep = (new FIFOIO) { Bool() }.flip
} }
class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component class rocketHTIF(w: Int)(implicit conf: CoherenceHubConfiguration) extends Component with ClientCoherenceAgent
{ {
val io = new Bundle { val io = new Bundle {
val host = new ioHost(w) val host = new ioHost(w)
val cpu = Vec(conf.ntiles) { new ioHTIF(conf.ntiles).flip } val cpu = Vec(conf.ln.nTiles) { new ioHTIF(conf.ln.nTiles).flip }
val mem = new ioTileLink val mem = new ioTileLink
} }
@@ -81,7 +81,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() } val cmd_readmem :: cmd_writemem :: cmd_readcr :: cmd_writecr :: cmd_ack :: cmd_nack :: Nil = Enum(6) { UFix() }
val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0) val pcr_addr = addr(io.cpu(0).pcr_req.bits.addr.width-1, 0)
val pcr_coreid = if (conf.ntiles == 1) UFix(0) else addr(20+log2Up(conf.ntiles),20) val pcr_coreid = if (conf.ln.nTiles == 1) UFix(0) else addr(20+log2Up(conf.ln.nTiles),20)
val pcr_wdata = packet_ram(0) val pcr_wdata = packet_ram(0)
val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR val bad_mem_packet = size(OFFSET_BITS-1-3,0).orR || addr(OFFSET_BITS-1-3,0).orR
@@ -193,8 +193,8 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
io.mem.probe_rep_data.valid := Bool(false) io.mem.probe_rep_data.valid := Bool(false)
io.mem.incoherent := Bool(true) io.mem.incoherent := Bool(true)
val pcrReadData = Vec(conf.ntiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } } val pcrReadData = Vec(conf.ln.nTiles) { Reg() { Bits(width = io.cpu(0).pcr_rep.bits.getWidth) } }
for (i <- 0 until conf.ntiles) { for (i <- 0 until conf.ln.nTiles) {
val my_reset = Reg(resetVal = Bool(true)) val my_reset = Reg(resetVal = Bool(true))
val my_ipi = Reg(resetVal = Bool(false)) val my_ipi = Reg(resetVal = Bool(false))
@@ -211,7 +211,7 @@ class rocketHTIF(w: Int)(implicit conf: UncoreConfiguration) extends Component
} }
cpu.ipi_rep.valid := my_ipi cpu.ipi_rep.valid := my_ipi
cpu.ipi_req.ready := Bool(true) cpu.ipi_req.ready := Bool(true)
for (j <- 0 until conf.ntiles) { for (j <- 0 until conf.ln.nTiles) {
when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) { when (io.cpu(j).ipi_req.valid && io.cpu(j).ipi_req.bits === UFix(i)) {
my_ipi := Bool(true) my_ipi := Bool(true)
} }

2
rocket/src/main/scala/nbdcache.scala
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@@ -858,7 +858,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
readArb.io.in(0).bits.way_en := Fix(-1) readArb.io.in(0).bits.way_en := Fix(-1)
// tag check and way muxing // tag check and way muxing
def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(i => f(i))){gen} def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(f)){gen}
val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> conf.untagbits)){Bits()}.toBits val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> conf.untagbits)){Bits()}.toBits
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && conf.co.isValid(meta.io.resp(w).state)){Bits()}.toBits val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && conf.co.isValid(meta.io.resp(w).state)){Bits()}.toBits
s1_clk_en := metaReadArb.io.out.valid s1_clk_en := metaReadArb.io.out.valid

2
rocket/src/main/scala/tile.scala
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@@ -21,7 +21,7 @@ case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
if (fastLoadByte) require(fastLoadWord) if (fastLoadByte) require(fastLoadWord)
} }
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
{ {
val memPorts = 2 + confIn.vec val memPorts = 2 + confIn.vec
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen) implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)