riscv/rocket-chip
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Refactored uncore conf

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Henry Cook committed 2013-01-07 13:41:36 -08:00
1 parent 78868f6075
commit 261e14f831
3 files changed
+8 -8
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rocket/src/main/scala/tile.scala
+1 -1
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@@ -21,7 +21,7 @@ case class RocketConfiguration(ntiles: Int, co: CoherencePolicyWithUncached,
if (fastLoadByte) require(fastLoadWord)
}
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal)
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Component(resetSignal) with ClientCoherenceAgent
{
val memPorts = 2 + confIn.vec
implicit val dcConf = confIn.dcache.copy(reqtagbits = confIn.dcacheReqTagBits + log2Up(memPorts), databits = confIn.xprlen)