riscv/rocket-chip
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Refactored uncore conf

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This commit is contained in:
Henry Cook
2012-12-13 11:45:42 -08:00
parent 78868f6075
commit 261e14f831
3 changed files with 8 additions and 8 deletions
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rocket/src/main/scala/nbdcache.scala
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@ -858,7 +858,7 @@ class HellaCache(implicit conf: DCacheConfig) extends Component {
readArb.io.in(0).bits.way_en := Fix(-1)
// tag check and way muxing
def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(i => f(i))){gen}
def wayMap[T <: Data](f: Int => T)(gen: => T) = Vec((0 until conf.ways).map(f)){gen}
val s1_tag_eq_way = wayMap((w: Int) => meta.io.resp(w).tag === (s1_addr >> conf.untagbits)){Bits()}.toBits
val s1_tag_match_way = wayMap((w: Int) => s1_tag_eq_way(w) && conf.co.isValid(meta.io.resp(w).state)){Bits()}.toBits
s1_clk_en := metaReadArb.io.out.valid