clean up caches
- remove incompatible blocking D$ - remove direct-mapped nonblocking cache
This commit is contained in:
Andrew Waterman
@ -650,282 +650,46 @@ class AMOALU extends Component {
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io.out := Mux(word, Cat(out(31,0), out(31,0)).toUFix, out)
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}
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class HellaCacheDM extends Component {
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val io = new ioDCacheHella()
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// interface between D$ and processor/DTLB
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class ioDmem(view: List[String] = null) extends Bundle(view) {
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val req_kill = Bool(INPUT);
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val req_val = Bool(INPUT);
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val req_rdy = Bool(OUTPUT);
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val req_cmd = Bits(4, INPUT);
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val req_type = Bits(3, INPUT);
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val req_idx = Bits(PGIDX_BITS, INPUT);
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val req_ppn = Bits(PPN_BITS, INPUT);
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val req_data = Bits(64, INPUT);
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val req_tag = Bits(DCACHE_TAG_BITS, INPUT);
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val xcpt_ma_ld = Bool(OUTPUT); // misaligned load
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val xcpt_ma_st = Bool(OUTPUT); // misaligned store
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val resp_miss = Bool(OUTPUT);
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val resp_nack = Bool(OUTPUT);
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val resp_val = Bool(OUTPUT);
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val resp_replay = Bool(OUTPUT);
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val resp_data = Bits(64, OUTPUT);
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val resp_data_subword = Bits(64, OUTPUT);
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val resp_tag = Bits(DCACHE_TAG_BITS, OUTPUT);
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}
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val lines = 1 << IDX_BITS
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val addrbits = PADDR_BITS
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val indexbits = log2up(lines)
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val offsetbits = OFFSET_BITS
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val tagmsb = PADDR_BITS-1
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val taglsb = indexbits+offsetbits
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val tagbits = tagmsb-taglsb+1
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val indexmsb = taglsb-1
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val indexlsb = offsetbits
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val offsetmsb = indexlsb-1
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val offsetlsb = log2up(CPU_DATA_BITS/8)
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val ramindexlsb = log2up(MEM_DATA_BITS/8)
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val early_nack = Reg { Bool() }
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val r_cpu_req_val_ = Reg(io.cpu.req_val && io.cpu.req_rdy, resetVal = Bool(false))
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val r_cpu_req_val = r_cpu_req_val_ && !io.cpu.req_kill && !early_nack
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val r_cpu_req_idx = Reg() { Bits() }
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val r_cpu_req_cmd = Reg() { Bits() }
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val r_cpu_req_type = Reg() { Bits() }
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val r_cpu_req_tag = Reg() { Bits() }
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val r_amo_replay_data = Reg() { Bits() }
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val p_store_valid = Reg(resetVal = Bool(false))
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val p_store_data = Reg() { Bits() }
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val p_store_idx = Reg() { Bits() }
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val p_store_cmd = Reg() { Bits() }
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val p_store_type = Reg() { Bits() }
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val r_replay_amo = Reg(resetVal = Bool(false))
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val req_store = (io.cpu.req_cmd === M_XWR)
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val req_load = (io.cpu.req_cmd === M_XRD)
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val req_amo = io.cpu.req_cmd(3).toBool
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val req_read = req_load || req_amo
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val req_write = req_store || req_amo
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val r_req_load = (r_cpu_req_cmd === M_XRD)
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val r_req_store = (r_cpu_req_cmd === M_XWR)
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val r_req_flush = (r_cpu_req_cmd === M_FLA)
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val r_req_fence = (r_cpu_req_cmd === M_FENCE)
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val r_req_amo = r_cpu_req_cmd(3).toBool
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val r_req_read = r_req_load || r_req_amo
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val r_req_write = r_req_store || r_req_amo
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val r_req_readwrite = r_req_read || r_req_write
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// replay unit
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val replayer = new ReplayUnit()
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val replay_amo_val = replayer.io.data_req.valid && replayer.io.data_req.bits.cmd(3).toBool
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when (io.cpu.req_val) {
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r_cpu_req_idx := io.cpu.req_idx
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r_cpu_req_cmd := io.cpu.req_cmd
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r_cpu_req_type := io.cpu.req_type
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r_cpu_req_tag := io.cpu.req_tag
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}
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when (replay_amo_val) {
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r_cpu_req_idx := Cat(replayer.io.data_req.bits.idx, replayer.io.data_req.bits.offset)
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r_cpu_req_cmd := replayer.io.data_req.bits.cmd
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r_cpu_req_type := replayer.io.data_req.bits.typ
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r_amo_replay_data := replayer.io.data_req.bits.data
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}
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val cpu_req_data = Mux(r_replay_amo, r_amo_replay_data, io.cpu.req_data)
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// refill counter
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val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val rr_count_next = rr_count + UFix(1)
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when (io.mem.resp_val) { rr_count := rr_count_next }
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val misaligned =
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(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && (r_cpu_req_idx(0) != Bits(0))) ||
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(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
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((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
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io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
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io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
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// tags
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val meta = new MetaDataArray(lines)
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val meta_arb = (new Arbiter(3)) { new MetaArrayReq() }
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meta_arb.io.out <> meta.io.req
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// data
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val data = new DataArray(lines)
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val data_arb = (new Arbiter(5)) { new DataArrayReq() }
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data_arb.io.out <> data.io.req
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// writeback unit
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val wb = new WritebackUnit
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val wb_arb = (new Arbiter(2)) { new WritebackReq() }
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wb_arb.io.out <> wb.io.req
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wb.io.data_req.bits.inner_req <> data_arb.io.in(3).bits
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wb.io.data_req.ready := data_arb.io.in(3).ready
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data_arb.io.in(3).valid := wb.io.data_req.valid
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wb.io.data_resp <> data.io.resp
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// cpu tag check
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meta_arb.io.in(2).valid := io.cpu.req_val
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meta_arb.io.in(2).bits.idx := io.cpu.req_idx(indexmsb,indexlsb)
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meta_arb.io.in(2).bits.rw := Bool(false)
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meta_arb.io.in(2).bits.data.valid := Bool(false) // don't care
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meta_arb.io.in(2).bits.data.dirty := Bool(false) // don't care
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meta_arb.io.in(2).bits.data.tag := UFix(0) // don't care
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val early_tag_nack = !meta_arb.io.in(2).ready
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val cpu_req_tag = Cat(io.cpu.req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
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val tag_match = meta.io.resp.valid && (meta.io.resp.tag === cpu_req_tag)
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val tag_hit = r_cpu_req_val && tag_match
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val tag_miss = r_cpu_req_val && !tag_match
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val dirty = meta.io.resp.valid && meta.io.resp.dirty
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// refill response
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val block_during_refill = !io.mem.resp_val && (rr_count != UFix(0))
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data_arb.io.in(0).valid := io.mem.resp_val || block_during_refill
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data_arb.io.in(0).bits.offset := rr_count
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data_arb.io.in(0).bits.rw := !block_during_refill
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data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
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data_arb.io.in(0).bits.data := io.mem.resp_data
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// load hits
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data_arb.io.in(4).bits.offset := io.cpu.req_idx(offsetmsb,ramindexlsb)
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data_arb.io.in(4).bits.idx := io.cpu.req_idx(indexmsb,indexlsb)
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data_arb.io.in(4).bits.rw := Bool(false)
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data_arb.io.in(4).bits.wmask := UFix(0) // don't care
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data_arb.io.in(4).bits.data := io.mem.resp_data // don't care
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data_arb.io.in(4).valid := io.cpu.req_val && req_read
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val early_load_nack = req_read && !data_arb.io.in(4).ready
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// store hits and AMO hits and misses use a pending store register.
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// we nack new stores if a pending store can't retire for some reason.
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// we drain a pending store if the CPU performs a store or a
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// conflictig load, or if the cache is idle, or after a miss.
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val p_store_idx_match = p_store_valid && (r_cpu_req_idx(indexmsb,indexlsb) === p_store_idx(indexmsb,indexlsb))
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val p_store_offset_match = (r_cpu_req_idx(indexlsb-1,offsetlsb) === p_store_idx(indexlsb-1,offsetlsb))
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val p_store_match = r_cpu_req_val && r_req_read && p_store_idx_match && p_store_offset_match
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val drain_store_val = (p_store_valid && (!io.cpu.req_val || !req_read || Reg(tag_miss))) || p_store_match
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data_arb.io.in(2).bits.offset := p_store_idx(offsetmsb,ramindexlsb)
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data_arb.io.in(2).bits.idx := p_store_idx(indexmsb,indexlsb)
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data_arb.io.in(2).bits.rw := Bool(true)
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data_arb.io.in(2).valid := drain_store_val
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val drain_store = drain_store_val && data_arb.io.in(2).ready
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val p_store_rdy = !p_store_valid || drain_store
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val p_amo = Reg(tag_hit && r_req_amo && p_store_rdy && !p_store_match || r_replay_amo, resetVal = Bool(false))
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p_store_valid := !p_store_rdy || (tag_hit && r_req_store) || p_amo
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// writeback
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val wb_rdy = wb_arb.io.in(1).ready && !p_store_idx_match
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wb_arb.io.in(1).valid := tag_miss && r_req_readwrite && dirty && !p_store_idx_match
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wb_arb.io.in(1).bits.ppn := meta.io.resp.tag
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wb_arb.io.in(1).bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
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// tag update after a miss or a store to an exclusive clean line.
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val clear_valid = tag_miss && r_req_readwrite && meta.io.resp.valid && (!dirty || wb_rdy)
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val set_dirty = tag_hit && !meta.io.resp.dirty && r_req_write
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meta.io.state_req.valid := clear_valid || set_dirty
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meta.io.state_req.bits.rw := Bool(true)
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meta.io.state_req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
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meta.io.state_req.bits.data.tag := UFix(0) // don't care
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meta.io.state_req.bits.data.valid := tag_match
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meta.io.state_req.bits.data.dirty := tag_match
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// pending store data, also used for AMO RHS
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val amoalu = new AMOALU
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when (tag_hit && r_req_write && p_store_rdy || r_replay_amo) {
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p_store_idx := r_cpu_req_idx
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p_store_type := r_cpu_req_type
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p_store_cmd := r_cpu_req_cmd
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p_store_data := cpu_req_data
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}
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when (p_amo) {
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p_store_data := amoalu.io.out
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}
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// miss handling
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val mshr = new MSHRFile()
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mshr.io.req_val := tag_miss && r_req_readwrite && (!dirty || wb_rdy) && (!r_req_write || replayer.io.sdq_enq.ready)
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mshr.io.req_ppn := cpu_req_tag
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mshr.io.req_idx := r_cpu_req_idx(indexmsb,indexlsb)
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mshr.io.req_tag := r_cpu_req_tag
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mshr.io.req_offset := r_cpu_req_idx(offsetmsb,0)
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mshr.io.req_cmd := r_cpu_req_cmd
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mshr.io.req_type := r_cpu_req_type
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mshr.io.req_sdq_id := replayer.io.sdq_id
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mshr.io.mem_resp_val := io.mem.resp_val && (~rr_count === UFix(0))
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mshr.io.mem_resp_tag := io.mem.resp_tag
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mshr.io.mem_req <> wb.io.refill_req
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mshr.io.meta_req.bits.inner_req <> meta_arb.io.in(1).bits
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mshr.io.meta_req.ready := meta_arb.io.in(1).ready
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meta_arb.io.in(1).valid := mshr.io.meta_req.valid
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mshr.io.replay <> replayer.io.replay
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replayer.io.sdq_enq.valid := tag_miss && r_req_write && (!dirty || wb_rdy) && mshr.io.req_rdy
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replayer.io.sdq_enq.bits := cpu_req_data
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data_arb.io.in(0).bits.idx := mshr.io.mem_resp_idx
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// replays
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val replay = replayer.io.data_req.bits
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val stall_replay = r_replay_amo || p_amo || p_store_valid
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val replay_val = replayer.io.data_req.valid && !stall_replay
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val replay_rdy = data_arb.io.in(1).ready
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data_arb.io.in(1).bits.offset := replay.offset(offsetmsb,ramindexlsb)
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data_arb.io.in(1).bits.idx := replay.idx
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data_arb.io.in(1).bits.rw := replay.cmd === M_XWR
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data_arb.io.in(1).valid := replay_val
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replayer.io.data_req.ready := replay_rdy && !stall_replay
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r_replay_amo := replay_amo_val && replay_rdy && !stall_replay
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// store write mask generation.
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// assumes store replays are higher-priority than pending stores.
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val maskgen = new StoreMaskGen
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val store_offset = Mux(!replay_val, p_store_idx(offsetmsb,0), replay.offset)
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maskgen.io.typ := Mux(!replay_val, p_store_type, replay.typ)
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maskgen.io.addr := store_offset(offsetlsb-1,0)
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val store_wmask_wide = maskgen.io.wmask << Cat(store_offset(ramindexlsb-1,offsetlsb), Bits(0, log2up(CPU_DATA_BITS/8))).toUFix
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val store_data = Mux(!replay_val, p_store_data, replay.data)
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val store_data_wide = Fill(MEM_DATA_BITS/CPU_DATA_BITS, store_data)
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data_arb.io.in(1).bits.data := store_data_wide
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data_arb.io.in(1).bits.wmask := store_wmask_wide
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data_arb.io.in(2).bits.data := store_data_wide
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data_arb.io.in(2).bits.wmask := store_wmask_wide
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// load data subword mux/sign extension.
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// subword loads are delayed by one cycle.
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val loadgen = new LoadDataGen
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val loadgen_use_replay = Reg(replay_val && replay_rdy)
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loadgen.io.typ := Mux(loadgen_use_replay, Reg(replay.typ), r_cpu_req_type)
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loadgen.io.addr := Mux(loadgen_use_replay, Reg(replay.offset), r_cpu_req_idx)(ramindexlsb-1,0)
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loadgen.io.din := data.io.resp
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amoalu.io.cmd := p_store_cmd
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amoalu.io.typ := p_store_type
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amoalu.io.lhs := loadgen.io.r_dout.toUFix
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amoalu.io.rhs := p_store_data.toUFix
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early_nack := early_tag_nack || early_load_nack || r_cpu_req_val && r_req_amo || replay_amo_val || r_replay_amo
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// reset and flush unit
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val flusher = new FlushUnit(lines)
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val flushed = Reg(resetVal = Bool(true))
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val flush_rdy = mshr.io.fence_rdy && wb_rdy && !p_store_valid
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flushed := flushed && !r_cpu_req_val || r_cpu_req_val && r_req_flush && flush_rdy && flusher.io.req.ready
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flusher.io.req.valid := r_cpu_req_val && r_req_flush && flush_rdy && !flushed
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flusher.io.wb_req <> wb_arb.io.in(0)
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flusher.io.meta_req.bits.inner_req <> meta_arb.io.in(0).bits
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flusher.io.meta_req.ready := meta_arb.io.in(0).ready
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meta_arb.io.in(0).valid := flusher.io.meta_req.valid
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flusher.io.meta_resp <> meta.io.resp
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flusher.io.resp.ready := Bool(true) // we don't respond to flush requests
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// we usually nack rather than reporting that the cache is not ready.
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// fences and flushes are the exceptions.
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val pending_fence = Reg(resetVal = Bool(false))
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pending_fence := (r_cpu_req_val && r_req_fence || pending_fence) && !flush_rdy
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val nack_hit = p_store_match || r_req_write && !p_store_rdy
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val nack_miss = dirty && !wb_rdy || !mshr.io.req_rdy || r_req_write && !replayer.io.sdq_enq.ready
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val nack_flush = !flush_rdy && (r_req_fence || r_req_flush) ||
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!flushed && r_req_flush
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val nack = early_nack || r_req_readwrite && Mux(tag_match, nack_hit, nack_miss) || nack_flush
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io.cpu.req_rdy := flusher.io.req.ready && !(r_cpu_req_val_ && r_req_flush) && !pending_fence
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io.cpu.resp_nack := r_cpu_req_val_ && !io.cpu.req_kill && nack
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io.cpu.resp_val := (tag_hit && !nack_hit && r_req_read) || replayer.io.cpu_resp_val
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io.cpu.resp_replay := replayer.io.cpu_resp_val
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io.cpu.resp_miss := tag_miss && !nack_miss && r_req_read
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io.cpu.resp_tag := Mux(replayer.io.cpu_resp_val, replayer.io.cpu_resp_tag, r_cpu_req_tag)
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io.cpu.resp_data := loadgen.io.dout
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io.cpu.resp_data_subword := loadgen.io.r_dout_subword
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wb.io.mem_req.ready := io.mem.req_rdy
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io.mem.req_val := wb.io.mem_req.valid
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io.mem.req_rw := wb.io.mem_req.bits.rw
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io.mem.req_wdata := wb.io.mem_req_data
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io.mem.req_tag := wb.io.mem_req.bits.tag.toUFix
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io.mem.req_addr := wb.io.mem_req.bits.addr
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// interface between D$ and next level in memory hierarchy
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class ioDCache(view: List[String] = null) extends Bundle(view) {
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val req_addr = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
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val req_tag = UFix(DMEM_TAG_BITS, INPUT);
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val req_val = Bool(INPUT);
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val req_rdy = Bool(OUTPUT);
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val req_wdata = Bits(MEM_DATA_BITS, INPUT);
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val req_rw = Bool(INPUT);
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val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
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val resp_tag = Bits(DMEM_TAG_BITS, OUTPUT);
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val resp_val = Bool(OUTPUT);
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}
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class HellaCacheAssoc extends Component {
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val io = new ioDCacheHella()
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class HellaCache extends Component {
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val io = new Bundle {
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val cpu = new ioDmem()
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val mem = new ioDCache().flip
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}
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||||
|
||||
val lines = 1 << IDX_BITS
|
||||
val addrbits = PADDR_BITS
|
||||
|
||||
Reference in New Issue
Block a user