diff --git a/rocket/src/main/scala/dcache.scala b/rocket/src/main/scala/dcache.scala
deleted file mode 100644
index 88aa3f3f..00000000
--- a/rocket/src/main/scala/dcache.scala
+++ /dev/null
@@ -1,517 +0,0 @@
-package Top {
-
-import Chisel._
-import Node._;
-import Constants._;
-import scala.math._;
-
-// interface between D$ and processor/DTLB
-class ioDmem(view: List[String] = null) extends Bundle(view) {
-  val req_kill  = Bool(INPUT);
-  val req_val   = Bool(INPUT);
-  val req_rdy   = Bool(OUTPUT);
-  val req_cmd   = Bits(4, INPUT);
-  val req_type  = Bits(3, INPUT);
-  val req_idx   = Bits(PGIDX_BITS, INPUT);
-  val req_ppn   = Bits(PPN_BITS, INPUT);
-  val req_data  = Bits(64, INPUT);
-  val req_tag   = Bits(DCACHE_TAG_BITS, INPUT);
-  val xcpt_ma_ld  = Bool(OUTPUT); // misaligned load
-  val xcpt_ma_st = Bool(OUTPUT); // misaligned store
-  val resp_miss = Bool(OUTPUT);
-  val resp_nack = Bool(OUTPUT);
-  val resp_val  = Bool(OUTPUT);
-  val resp_replay = Bool(OUTPUT);
-  val resp_data = Bits(64, OUTPUT);
-  val resp_data_subword = Bits(64, OUTPUT);
-  val resp_tag  = Bits(DCACHE_TAG_BITS, OUTPUT);
-}
-
-// interface between D$ and next level in memory hierarchy
-class ioDCache(view: List[String] = null) extends Bundle(view) {
-  val req_addr  = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
-  val req_tag   = UFix(DMEM_TAG_BITS, INPUT);
-  val req_val   = Bool(INPUT);
-  val req_rdy   = Bool(OUTPUT);
-  val req_wdata = Bits(MEM_DATA_BITS, INPUT);
-  val req_rw    = Bool(INPUT);
-  val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
-  val resp_tag  = Bits(DMEM_TAG_BITS, OUTPUT);
-  val resp_val  = Bool(OUTPUT);
-}
-
-class ioDCacheDM extends Bundle() {
-  val cpu = new ioDmem();
-  val mem = new ioDCache().flip();
-}
-
-class ioDCacheHella extends Bundle() {
-  val cpu = new ioDmem();
-  val mem = new ioDCache().flip();
-}
-
-class rocketDCacheStoreGen extends Component {
-  val io = new Bundle {
-    val req_type      = Bits(3, INPUT);
-    val req_addr_lsb  = Bits(3, INPUT);
-    val req_data      = Bits(64, INPUT);
-    val store_wmask   = Bits(64, OUTPUT);
-    val store_data    = Bits(64, OUTPUT);
-  }
-  
-  // generate write mask and store data signals based on store type and address LSBs
-  val wmask_b =
-    Mux(io.req_addr_lsb === UFix(0, 3), Bits("b0000_0001", 8),
-    Mux(io.req_addr_lsb === UFix(1, 3), Bits("b0000_0010", 8),
-    Mux(io.req_addr_lsb === UFix(2, 3), Bits("b0000_0100", 8),
-    Mux(io.req_addr_lsb === UFix(3, 3), Bits("b0000_1000", 8),
-    Mux(io.req_addr_lsb === UFix(4, 3), Bits("b0001_0000", 8),
-    Mux(io.req_addr_lsb === UFix(5, 3), Bits("b0010_0000", 8),
-    Mux(io.req_addr_lsb === UFix(6, 3), Bits("b0100_0000", 8),
-    Mux(io.req_addr_lsb === UFix(7, 3), Bits("b1000_0000", 8),
-        UFix(0, 8)))))))));
-
-  val wmask_h =
-    Mux(io.req_addr_lsb(2,1) === UFix(0, 2), Bits("b0000_0011", 8),
-    Mux(io.req_addr_lsb(2,1) === UFix(1, 2), Bits("b0000_1100", 8),
-    Mux(io.req_addr_lsb(2,1) === UFix(2, 2), Bits("b0011_0000", 8),
-    Mux(io.req_addr_lsb(2,1) === UFix(3, 2), Bits("b1100_0000", 8),
-        UFix(0, 8)))));
-
-  val wmask_w =
-    Mux(io.req_addr_lsb(2) === UFix(0, 1), Bits("b0000_1111", 8),
-    Mux(io.req_addr_lsb(2) === UFix(1, 1), Bits("b1111_0000", 8),
-        UFix(0, 8)));
-
-  val wmask_d =
-    Bits("b1111_1111", 8);
-    
-  val store_wmask_byte =
-    Mux(io.req_type === MT_B, wmask_b,
-    Mux(io.req_type === MT_H, wmask_h,
-    Mux(io.req_type === MT_W, wmask_w,
-    Mux(io.req_type === MT_D, wmask_d,
-        UFix(0, 8)))));
-  
-  val store_wmask_d = Cat(Fill(8, store_wmask_byte(7)),
-  		Fill(8, store_wmask_byte(6)),
-  		Fill(8, store_wmask_byte(5)),
-  		Fill(8, store_wmask_byte(4)),
-  		Fill(8, store_wmask_byte(3)),
-  		Fill(8, store_wmask_byte(2)),
-  		Fill(8, store_wmask_byte(1)),
-  		Fill(8, store_wmask_byte(0)));
-  
-  io.store_wmask := store_wmask_d;
-  
-  io.store_data :=
-    Mux(io.req_type === MT_B, Fill(8, io.req_data( 7,0)),
-    Mux(io.req_type === MT_H, Fill(4, io.req_data(15,0)),
-    Mux(io.req_type === MT_W, Fill(2, io.req_data(31,0)),
-    Mux(io.req_type === MT_D, io.req_data,
-       UFix(0, 64)))));  
-  
-}
- 
-// state machine to flush (write back dirty lines, invalidate clean ones) the D$
-class rocketDCacheDM_flush(lines: Int) extends Component {
-  val io = new ioDCacheDM();
-  val dcache = new rocketDCacheDM(lines);
-  
-  val addrbits = PADDR_BITS;
-  val indexbits = ceil(log10(lines)/log10(2)).toInt;
-  val offsetbits = 6;
-  val tagmsb    = addrbits - 1;
-  val taglsb    = indexbits+offsetbits;
-  val tagbits   = tagmsb-taglsb+1;
-  val indexmsb  = taglsb-1;
-  val indexlsb  = offsetbits;
-  val offsetmsb = indexlsb-1;
-  val offsetlsb = 3;
-  
-  val flush_count = Reg(resetVal = UFix(0, indexbits));
-  val flush_resp_count = Reg(resetVal = UFix(0, indexbits));
-  val flushing = Reg(resetVal = Bool(false));
-  val flush_waiting = Reg(resetVal = Bool(false));
-  val r_cpu_req_tag = Reg() { Bits() }
-
-  when (io.cpu.req_val && io.cpu.req_rdy && (io.cpu.req_cmd === M_FLA)) 
-  { 
-    r_cpu_req_tag := io.cpu.req_tag;
-    flushing := Bool(true);
-    flush_waiting := Bool(true);
-  }
-  
-  when (dcache.io.cpu.req_rdy && (flush_count === ~Bits(0, indexbits))) {
-    flushing := Bool(false);
-  }
-  when (dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag) && (flush_resp_count === ~Bits(0, indexbits))) {
-    flush_waiting := Bool(false);
-  }
-  
-  when (flushing && dcache.io.cpu.req_rdy) {
-    flush_count := flush_count + UFix(1,1);
-  }
-  when (flush_waiting && dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag)) {
-    flush_resp_count := flush_resp_count + UFix(1,1);
-  }
-  
-  dcache.io.cpu.req_val   := (io.cpu.req_val && (io.cpu.req_cmd != M_FLA) && !flush_waiting) || flushing;
-  dcache.io.cpu.req_cmd   := Mux(flushing, M_FLA, io.cpu.req_cmd);
-  dcache.io.cpu.req_idx   := Mux(flushing, Cat(flush_count, Bits(0,offsetbits)), io.cpu.req_idx);
-  dcache.io.cpu.req_ppn   := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn);
-  dcache.io.cpu.req_tag   := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
-  dcache.io.cpu.req_type  := io.cpu.req_type;
-  dcache.io.cpu.req_data  <> io.cpu.req_data;
-  dcache.io.cpu.req_kill  := io.cpu.req_kill && !flush_waiting;
-  dcache.io.mem           <> io.mem;
-
-  io.cpu.xcpt_ma_ld   := dcache.io.cpu.xcpt_ma_ld;
-  io.cpu.xcpt_ma_st   := dcache.io.cpu.xcpt_ma_st;
-  io.cpu.req_rdy   := dcache.io.cpu.req_rdy && !flush_waiting;
-  io.cpu.resp_miss := dcache.io.cpu.resp_miss;
-  io.cpu.resp_nack := dcache.io.cpu.resp_nack;
-  io.cpu.resp_data := dcache.io.cpu.resp_data;
-  io.cpu.resp_tag  := dcache.io.cpu.resp_tag;
-  io.cpu.resp_val  := dcache.io.cpu.resp_val & 
-    !(flush_waiting && (io.cpu.resp_tag === r_cpu_req_tag) && (flush_count != ~Bits(0, addrbits)));
-  
-}
-
-class rocketDCacheDM(lines: Int) extends Component {
-  val io = new ioDCacheDM();
-  
-  val addrbits = PADDR_BITS;
-  val indexbits = ceil(log10(lines)/log10(2)).toInt;
-  val offsetbits = 6; // 64 byte cache lines = 2^6 bytes
-  val tagmsb    = PADDR_BITS-1;
-  val taglsb    = indexbits+offsetbits;
-  val tagbits   = tagmsb-taglsb+1;
-  val indexmsb  = taglsb-1;
-  val indexlsb  = offsetbits;
-  val offsetmsb = indexlsb-1;
-  val offsetlsb = 3;
-  
-  val s_reset :: s_ready :: s_replay_load :: s_write_amo :: s_start_writeback :: s_writeback :: s_req_refill :: s_refill :: s_resolve_miss :: Nil = Enum(9) { UFix() };
-  val state = Reg(resetVal = s_reset);
-  
-  // idx arrives one clock cycle prior to ppn b/c of DTLB
-  val r_cpu_req_idx    = Reg(resetVal = Bits(0, PGIDX_BITS)); 
-  val r_cpu_req_ppn    = Reg(resetVal = Bits(0, PPN_BITS)); 
-  val r_cpu_req_val    = Reg(resetVal = Bool(false));
-  val r_cpu_req_cmd    = Reg(resetVal = Bits(0,4));
-  val r_cpu_req_type   = Reg(resetVal = Bits(0,3));
-  val r_cpu_req_tag    = Reg() { Bits() }
-  val r_cpu_resp_val   = Reg(resetVal = Bool(false));
-  val r_amo_data       = Reg(resetVal = Bits(0,64));
-
-  val p_store_data      = Reg(resetVal = Bits(0,64));
-  val p_store_idx       = Reg(resetVal = Bits(0,PGIDX_BITS));
-  val p_store_type      = Reg(resetVal = Bits(0,3));
-  val p_store_valid     = Reg(resetVal = Bool(false));
-
-  val req_store   = (io.cpu.req_cmd === M_XWR);
-  val req_load    = (io.cpu.req_cmd === M_XRD);
-  val req_flush   = (io.cpu.req_cmd === M_FLA);
-  val req_amo     = io.cpu.req_cmd(3).toBool;
-  val r_req_load  = (r_cpu_req_cmd === M_XRD);
-  val r_req_store = (r_cpu_req_cmd === M_XWR);
-  val r_req_flush = (r_cpu_req_cmd === M_FLA);
-  val r_req_amo     = r_cpu_req_cmd(3).toBool;
-  
-  when (io.cpu.req_val && io.cpu.req_rdy) {
-    r_cpu_req_idx   := io.cpu.req_idx;
-    r_cpu_req_cmd   := io.cpu.req_cmd;
-    r_cpu_req_type  := io.cpu.req_type;
-    r_cpu_req_tag   := io.cpu.req_tag;
-  }
-  
-  when ((state === s_ready) && r_cpu_req_val && !io.cpu.req_kill) {
-    r_cpu_req_ppn := io.cpu.req_ppn;
-  }
-  when (io.cpu.req_rdy) {
-    r_cpu_req_val := io.cpu.req_val; 
-  }
-  otherwise {
-    r_cpu_req_val := Bool(false);
-  }
-  when (((state === s_resolve_miss) && (r_req_load || r_req_amo)) || (state === s_replay_load)) {
-    r_cpu_resp_val := Bool(true);
-  }
-  otherwise {
-    r_cpu_resp_val := Bool(false);
-  }
-  
-  // refill counter
-  val rr_count = Reg(resetVal = UFix(0,2));
-  val rr_count_next = rr_count + UFix(1);
-  when (((state === s_refill) && io.mem.resp_val) || ((state === s_writeback) && io.mem.req_rdy)) { 
-    rr_count := rr_count_next;
-  }
-
-  // tag array
-  val tag_addr = 
-    Mux((state === s_ready), io.cpu.req_idx(PGIDX_BITS-1,offsetbits),
-      r_cpu_req_idx(PGIDX_BITS-1,offsetbits)).toUFix;  
-  val tag_we = 
-    ((state === s_refill) && io.mem.resp_val && (rr_count === UFix(3,2))) ||
-    ((state === s_resolve_miss) && r_req_flush);
-
-  val tag_array = Mem(lines, r_cpu_req_ppn);
-  tag_array.setReadLatency(1);
-  tag_array.setTarget('inst);
-  val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
-
-  // valid bit array
-  val vb_array = Reg(resetVal = Bits(0, lines));
-  when (tag_we && !r_req_flush) { 
-    vb_array := vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
-  }
-  when (tag_we && r_req_flush) {
-    vb_array := vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
-  }
-  val vb_rdata = vb_array(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix).toBool;
-  val tag_valid = r_cpu_req_val && vb_rdata;
-  val tag_match = (tag_rdata === io.cpu.req_ppn);
-  val tag_hit  = tag_valid && tag_match;
-  val miss = r_cpu_req_val && (!vb_rdata || !tag_match);
-
-  // load/store addresses conflict if they are to any part of the same 64 bit word
-  val addr_match    = (r_cpu_req_idx(PGIDX_BITS-1,offsetlsb) === p_store_idx(PGIDX_BITS-1,offsetlsb));
-  val ldst_conflict = tag_valid && tag_match && (r_req_load || r_req_amo) && p_store_valid && addr_match;
-  val store_hit = r_cpu_req_val && !io.cpu.req_kill && tag_hit && r_req_store ;
-
-  // write the pending store data when the cache is idle, when the next command isn't a load
-  // or when there's a load to the same address (in which case there's a 2 cycle delay:
-  // once cycle to write the store data and another to read the data back)
-  val drain_store = 
-    ((store_hit || p_store_valid) && (!io.cpu.req_val || req_store || req_flush)) ||
-    (p_store_valid && (miss || ldst_conflict));
-
-  // write pending store data from a store which missed
-  // after the cache line refill has completed
-  val resolve_store = (state === s_resolve_miss) && r_req_store;
-  
-  // pending store data
-  when (io.cpu.req_val && io.cpu.req_rdy && req_store) { 
-    p_store_idx   := io.cpu.req_idx;
-    p_store_data  := io.cpu.req_data;
-    p_store_type  := io.cpu.req_type;
-  }
-  when (store_hit && !drain_store) {
-    p_store_valid := Bool(true);
-  }
-  when (drain_store)  {
-    p_store_valid := Bool(false);
-  }
-  
-  // AMO operand
-  when (io.cpu.req_val && io.cpu.req_rdy && req_amo) {
-    r_amo_data := io.cpu.req_data;
-  }
-
-  // dirty bit array
-  val db_array  = Reg(resetVal = Bits(0, lines));
-  val tag_dirty = db_array(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix).toBool;  
-  when ((r_cpu_req_val && !io.cpu.req_kill && tag_hit && r_req_store) || resolve_store)  {
-    db_array := db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
-  }
-  when (state === s_write_amo) {
-    db_array := db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
-  }
-  when (tag_we) {
-    db_array := db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
-  }
-  
-  // generate write mask and data signals for stores and amos
-  val storegen = new rocketDCacheStoreGen();
-  storegen.io.req_addr_lsb := p_store_idx(2,0);
-  storegen.io.req_data := p_store_data;
-  storegen.io.req_type := p_store_type;
-  val store_data = Fill(2, storegen.io.store_data);
-  val store_wmask_d = storegen.io.store_wmask;
-  val store_wmask = Mux(p_store_idx(offsetlsb).toBool, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d)); 
-
-  // ALU for AMOs
-  val amo_alu = new rocketDCacheAmoALU();
-  val amo_alu_out = Cat(amo_alu.io.result,amo_alu.io.result);
-  val amo_wmask = 
-    Mux(r_cpu_req_type === MT_D, ~Bits(0,8),
-    Mux(r_cpu_req_idx(2).toBool, Cat(~Bits(0,4), Bits(0,4)),
-      Cat(Bits(0,4), ~Bits(0,4))));
-
-  val amo_store_wmask_d = Cat(Fill(8, amo_wmask(7)),
-  		Fill(8, amo_wmask(6)),
-  		Fill(8, amo_wmask(5)),
-  		Fill(8, amo_wmask(4)),
-  		Fill(8, amo_wmask(3)),
-  		Fill(8, amo_wmask(2)),
-  		Fill(8, amo_wmask(1)),
-  		Fill(8, amo_wmask(0)));
-
-  val amo_store_wmask = Mux(r_cpu_req_idx(offsetlsb).toBool, Cat(amo_store_wmask_d, Bits(0,64)), Cat(Bits(0,64), amo_store_wmask_d)); 
-  
-  // data array
-  val data_addr = 
-    Mux(drain_store || resolve_store, p_store_idx(PGIDX_BITS-1, offsetmsb-1),
-    Mux((state === s_writeback) && io.mem.req_rdy, Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count_next),
-    Mux((state === s_start_writeback) || (state === s_writeback) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count),
-    Mux((state === s_resolve_miss) || (state === s_replay_load) || (state === s_write_amo),  r_cpu_req_idx(PGIDX_BITS-1, offsetmsb-1),
-      io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1))))).toUFix;
-      
-  val data_wdata = 
-    Mux((state === s_refill), io.mem.resp_data, 
-    Mux((state === s_write_amo), amo_alu_out,
-      store_data));
-     
-  val data_we =
-    ((state === s_refill) && io.mem.resp_val) ||
-    (state === s_write_amo) ||
-     drain_store || resolve_store;
-     
-  val data_wmask =
-    Mux((state === s_refill), ~Bits(0,128),
-    Mux((state === s_write_amo), amo_store_wmask,
-      store_wmask));
-
-  val data_array = Mem(lines*4, data_wdata);
-  data_array.setReadLatency(1);
-  data_array.setTarget('inst);
-  val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask);
-  val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
-  val r_resp_data = Reg(resp_data);
-
-  amo_alu.io.cmd := r_cpu_req_cmd;
-  amo_alu.io.wmask := amo_wmask;
-  amo_alu.io.lhs := Mux(r_cpu_resp_val, resp_data, r_resp_data).toUFix;
-  amo_alu.io.rhs := r_amo_data.toUFix;
-
-  // signal a load miss when the data isn't present in the cache and when it's in the pending store data register
-  // (causes the cache to block for 2 cycles and the load or amo instruction is replayed)
-  val load_miss = 
-    !io.cpu.req_kill && 
-    (state === s_ready) && r_cpu_req_val && (r_req_load || r_req_amo) && (!tag_hit || (p_store_valid && addr_match));
-
-  // output signals
-  // busy when there's a load to the same address as a pending store, or on a cache miss, or when executing a flush
-  io.cpu.req_rdy   := (state === s_ready) && !io.cpu.req_kill && !ldst_conflict && (!r_cpu_req_val || (tag_hit && !(r_req_flush || r_req_amo)));
-  io.cpu.resp_val  := !io.cpu.req_kill && 
-                      ((state === s_ready) &&  tag_hit && (r_req_load || r_req_amo) && !(p_store_valid && addr_match)) || 
-                      ((state === s_resolve_miss) && r_req_flush) ||
-                      r_cpu_resp_val;
-                      
-  val misaligned =
-    (((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && r_cpu_req_idx(0).toBool) ||
-    (((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
-    ((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
-    
-  io.cpu.xcpt_ma_ld := r_cpu_req_val && (r_req_load  || r_req_amo) && misaligned;
-  io.cpu.xcpt_ma_st := r_cpu_req_val && (r_req_store || r_req_amo) && misaligned;
-    
-  io.cpu.resp_miss := load_miss;
-  io.cpu.resp_nack := Bool(false)
-  io.cpu.resp_tag  := r_cpu_req_tag
-  io.cpu.resp_data := resp_data;
-
-  io.mem.req_val   := (state === s_req_refill) || (state === s_writeback);
-  io.mem.req_rw    := (state === s_writeback);
-  io.mem.req_wdata := data_array_rdata;
-  io.mem.req_tag   := UFix(0);
-  io.mem.req_addr  := 
-    Mux(state === s_writeback, Cat(tag_rdata, r_cpu_req_idx(PGIDX_BITS-1, offsetbits)), 
-      Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits))).toUFix;
-
-  // control state machine
-  switch (state) {
-    is (s_reset) {
-      state := s_ready;
-    }
-    is (s_ready) {
-      when (io.cpu.req_kill) {
-        state := s_ready;
-      }
-      when (ldst_conflict) {
-        state := s_replay_load;
-      }
-      when (!r_cpu_req_val || (tag_hit && !(r_req_flush || r_req_amo))) {
-        state := s_ready;
-      }
-      when (tag_hit && r_req_amo) {
-        state := s_write_amo;
-      }
-      when (tag_valid & tag_dirty) {
-        state := s_start_writeback; 
-      }
-      when (r_req_flush) {
-        state := s_resolve_miss;
-      }
-      otherwise {
-        state := s_req_refill;
-      }
-    }
-    is (s_replay_load) {
-      state := s_ready;
-    }
-    is (s_write_amo) {
-      state := s_ready;
-    }
-    is (s_start_writeback) {
-      state := s_writeback;
-    }
-    is (s_writeback) {
-      when (io.mem.req_rdy && (rr_count === UFix(3,2))) { 
-        when (r_req_flush) {
-          state := s_resolve_miss;
-        } 
-        otherwise {
-          state := s_req_refill;
-        }
-      }
-    }
-    is (s_req_refill)
-    {
-      when (io.mem.req_rdy) { state := s_refill; }
-    }
-    is (s_refill) {
-      when (io.mem.resp_val && (rr_count === UFix(3,2))) { state := s_resolve_miss; }
-    }
-    is (s_resolve_miss) {
-      when (r_req_amo) {
-        state := s_write_amo;
-      }
-      state := s_ready;
-    }
-  }  
-}
-
-class rocketDCacheAmoALU extends Component {
-  val io = new Bundle {
-    val cmd  = Bits(4, INPUT);
-    val wmask = Bits(8, INPUT);
-    val lhs   = UFix(64, INPUT);
-    val rhs   = UFix(64, INPUT);
-    val result    = UFix(64, OUTPUT);
-  }
-  
-//   val signed_cmp = (op === M_XA_MIN) || (op === M_XA_MAX);
-//   val sub = (op === M_XA_MIN) || (op === M_XA_MINU) ||
-//             (op === M_XA_MAX) || (op === M_XA_MAXU);
-
-  val adder_lhs = Cat(io.lhs(63,32),io.wmask(3) & io.lhs(31), io.lhs(30,0)).toUFix;
-  val adder_rhs = Cat(io.rhs(63,32),io.wmask(3) & io.rhs(31), io.rhs(30,0)).toUFix;
-//   val adder_rhs = Cat(Mux(sub, ~io.rhs, io.rhs), sub).toUFix;
-//   val sum = adder_lhs + adder_rhs;
-//   val adder_out = sum(64,1);
-  val adder_out = adder_lhs + adder_rhs;
-  val alu_out = Wire() { UFix() };
-  switch (io.cmd) {
-//     is (M_XA_ADD)  { alu_out := adder_out; }
-    is (M_XA_SWAP) { alu_out := io.rhs; }
-    is (M_XA_AND)  { alu_out := io.lhs & io.rhs; }
-    is (M_XA_OR)   { alu_out := io.lhs | io.rhs; }
-  }
-  alu_out := adder_out;
-  io.result := alu_out;
-}
-  
-}
diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala
index a7cd6748..2582ce0e 100644
--- a/rocket/src/main/scala/nbdcache.scala
+++ b/rocket/src/main/scala/nbdcache.scala
@@ -650,282 +650,46 @@ class AMOALU extends Component {
   io.out := Mux(word, Cat(out(31,0), out(31,0)).toUFix, out)
 }
 
-class HellaCacheDM extends Component {
-  val io = new ioDCacheHella()
+// interface between D$ and processor/DTLB
+class ioDmem(view: List[String] = null) extends Bundle(view) {
+  val req_kill  = Bool(INPUT);
+  val req_val   = Bool(INPUT);
+  val req_rdy   = Bool(OUTPUT);
+  val req_cmd   = Bits(4, INPUT);
+  val req_type  = Bits(3, INPUT);
+  val req_idx   = Bits(PGIDX_BITS, INPUT);
+  val req_ppn   = Bits(PPN_BITS, INPUT);
+  val req_data  = Bits(64, INPUT);
+  val req_tag   = Bits(DCACHE_TAG_BITS, INPUT);
+  val xcpt_ma_ld  = Bool(OUTPUT); // misaligned load
+  val xcpt_ma_st = Bool(OUTPUT); // misaligned store
+  val resp_miss = Bool(OUTPUT);
+  val resp_nack = Bool(OUTPUT);
+  val resp_val  = Bool(OUTPUT);
+  val resp_replay = Bool(OUTPUT);
+  val resp_data = Bits(64, OUTPUT);
+  val resp_data_subword = Bits(64, OUTPUT);
+  val resp_tag  = Bits(DCACHE_TAG_BITS, OUTPUT);
+}
 
-  val lines       = 1 << IDX_BITS
-  val addrbits    = PADDR_BITS
-  val indexbits   = log2up(lines)
-  val offsetbits  = OFFSET_BITS
-  val tagmsb      = PADDR_BITS-1
-  val taglsb      = indexbits+offsetbits
-  val tagbits     = tagmsb-taglsb+1
-  val indexmsb    = taglsb-1
-  val indexlsb    = offsetbits
-  val offsetmsb   = indexlsb-1
-  val offsetlsb   = log2up(CPU_DATA_BITS/8)
-  val ramindexlsb = log2up(MEM_DATA_BITS/8)
-  
-  val early_nack       = Reg { Bool() }
-  val r_cpu_req_val_   = Reg(io.cpu.req_val && io.cpu.req_rdy, resetVal = Bool(false))
-  val r_cpu_req_val    = r_cpu_req_val_ && !io.cpu.req_kill && !early_nack
-  val r_cpu_req_idx    = Reg() { Bits() }
-  val r_cpu_req_cmd    = Reg() { Bits() }
-  val r_cpu_req_type   = Reg() { Bits() }
-  val r_cpu_req_tag    = Reg() { Bits() }
-  val r_amo_replay_data = Reg() { Bits() }
-
-  val p_store_valid    = Reg(resetVal = Bool(false))
-  val p_store_data     = Reg() { Bits() }
-  val p_store_idx      = Reg() { Bits() }
-  val p_store_cmd      = Reg() { Bits() }
-  val p_store_type     = Reg() { Bits() }
-  val r_replay_amo     = Reg(resetVal = Bool(false))
-
-  val req_store   = (io.cpu.req_cmd === M_XWR)
-  val req_load    = (io.cpu.req_cmd === M_XRD)
-  val req_amo     = io.cpu.req_cmd(3).toBool
-  val req_read    = req_load || req_amo
-  val req_write   = req_store || req_amo
-  val r_req_load  = (r_cpu_req_cmd === M_XRD)
-  val r_req_store = (r_cpu_req_cmd === M_XWR)
-  val r_req_flush = (r_cpu_req_cmd === M_FLA)
-  val r_req_fence = (r_cpu_req_cmd === M_FENCE)
-  val r_req_amo   = r_cpu_req_cmd(3).toBool
-  val r_req_read  = r_req_load || r_req_amo
-  val r_req_write = r_req_store || r_req_amo
-  val r_req_readwrite = r_req_read || r_req_write
-
-  // replay unit
-  val replayer = new ReplayUnit()
-  val replay_amo_val = replayer.io.data_req.valid && replayer.io.data_req.bits.cmd(3).toBool
-  
-  when (io.cpu.req_val) {
-    r_cpu_req_idx  := io.cpu.req_idx
-    r_cpu_req_cmd  := io.cpu.req_cmd
-    r_cpu_req_type := io.cpu.req_type
-    r_cpu_req_tag  := io.cpu.req_tag
-  }
-  when (replay_amo_val) {
-    r_cpu_req_idx  := Cat(replayer.io.data_req.bits.idx, replayer.io.data_req.bits.offset)
-    r_cpu_req_cmd  := replayer.io.data_req.bits.cmd
-    r_cpu_req_type := replayer.io.data_req.bits.typ
-    r_amo_replay_data := replayer.io.data_req.bits.data
-  }
-  val cpu_req_data = Mux(r_replay_amo, r_amo_replay_data, io.cpu.req_data)
-
-  // refill counter
-  val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
-  val rr_count_next = rr_count + UFix(1)
-  when (io.mem.resp_val) { rr_count := rr_count_next }
-
-  val misaligned =
-    (((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && (r_cpu_req_idx(0) != Bits(0))) ||
-    (((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
-    ((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
-    
-  io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
-  io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
-
-  // tags
-  val meta = new MetaDataArray(lines)
-  val meta_arb = (new Arbiter(3)) { new MetaArrayReq() }
-  meta_arb.io.out <> meta.io.req
-
-  // data
-  val data = new DataArray(lines)
-  val data_arb = (new Arbiter(5)) { new DataArrayReq() }
-  data_arb.io.out <> data.io.req
-
-  // writeback unit
-  val wb = new WritebackUnit
-  val wb_arb = (new Arbiter(2)) { new WritebackReq() }
-  wb_arb.io.out <> wb.io.req
-  wb.io.data_req.bits.inner_req <> data_arb.io.in(3).bits 
-  wb.io.data_req.ready := data_arb.io.in(3).ready
-  data_arb.io.in(3).valid := wb.io.data_req.valid
-  wb.io.data_resp <> data.io.resp
-
-  // cpu tag check
-  meta_arb.io.in(2).valid := io.cpu.req_val
-  meta_arb.io.in(2).bits.idx := io.cpu.req_idx(indexmsb,indexlsb)
-  meta_arb.io.in(2).bits.rw := Bool(false)
-  meta_arb.io.in(2).bits.data.valid := Bool(false) // don't care
-  meta_arb.io.in(2).bits.data.dirty := Bool(false) // don't care
-  meta_arb.io.in(2).bits.data.tag := UFix(0)       // don't care
-  val early_tag_nack = !meta_arb.io.in(2).ready
-  val cpu_req_tag = Cat(io.cpu.req_ppn, r_cpu_req_idx)(tagmsb,taglsb)
-  val tag_match = meta.io.resp.valid && (meta.io.resp.tag === cpu_req_tag)
-  val tag_hit  = r_cpu_req_val &&  tag_match
-  val tag_miss = r_cpu_req_val && !tag_match
-  val dirty = meta.io.resp.valid && meta.io.resp.dirty
-
-  // refill response
-  val block_during_refill = !io.mem.resp_val && (rr_count != UFix(0))
-  data_arb.io.in(0).valid := io.mem.resp_val || block_during_refill
-  data_arb.io.in(0).bits.offset := rr_count
-  data_arb.io.in(0).bits.rw := !block_during_refill
-  data_arb.io.in(0).bits.wmask := ~UFix(0, MEM_DATA_BITS/8)
-  data_arb.io.in(0).bits.data := io.mem.resp_data
-
-  // load hits
-  data_arb.io.in(4).bits.offset := io.cpu.req_idx(offsetmsb,ramindexlsb)
-  data_arb.io.in(4).bits.idx := io.cpu.req_idx(indexmsb,indexlsb)
-  data_arb.io.in(4).bits.rw := Bool(false)
-  data_arb.io.in(4).bits.wmask := UFix(0) // don't care
-  data_arb.io.in(4).bits.data := io.mem.resp_data // don't care
-  data_arb.io.in(4).valid := io.cpu.req_val && req_read
-  val early_load_nack = req_read && !data_arb.io.in(4).ready
-
-  // store hits and AMO hits and misses use a pending store register.
-  // we nack new stores if a pending store can't retire for some reason.
-  // we drain a pending store if the CPU performs a store or a
-  // conflictig load, or if the cache is idle, or after a miss.
-  val p_store_idx_match = p_store_valid && (r_cpu_req_idx(indexmsb,indexlsb) === p_store_idx(indexmsb,indexlsb))
-  val p_store_offset_match = (r_cpu_req_idx(indexlsb-1,offsetlsb) === p_store_idx(indexlsb-1,offsetlsb))
-  val p_store_match = r_cpu_req_val && r_req_read && p_store_idx_match && p_store_offset_match
-  val drain_store_val = (p_store_valid && (!io.cpu.req_val || !req_read || Reg(tag_miss))) || p_store_match
-  data_arb.io.in(2).bits.offset := p_store_idx(offsetmsb,ramindexlsb)
-  data_arb.io.in(2).bits.idx := p_store_idx(indexmsb,indexlsb)
-  data_arb.io.in(2).bits.rw := Bool(true)
-  data_arb.io.in(2).valid := drain_store_val
-  val drain_store = drain_store_val && data_arb.io.in(2).ready
-  val p_store_rdy = !p_store_valid || drain_store
-  val p_amo = Reg(tag_hit && r_req_amo && p_store_rdy && !p_store_match || r_replay_amo, resetVal = Bool(false))
-  p_store_valid := !p_store_rdy || (tag_hit && r_req_store) || p_amo
-
-  // writeback
-  val wb_rdy = wb_arb.io.in(1).ready && !p_store_idx_match
-  wb_arb.io.in(1).valid := tag_miss && r_req_readwrite && dirty && !p_store_idx_match
-  wb_arb.io.in(1).bits.ppn := meta.io.resp.tag
-  wb_arb.io.in(1).bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
-
-  // tag update after a miss or a store to an exclusive clean line.
-  val clear_valid = tag_miss && r_req_readwrite && meta.io.resp.valid && (!dirty || wb_rdy)
-  val set_dirty   = tag_hit && !meta.io.resp.dirty && r_req_write
-  meta.io.state_req.valid := clear_valid || set_dirty
-  meta.io.state_req.bits.rw := Bool(true)
-  meta.io.state_req.bits.idx := r_cpu_req_idx(indexmsb,indexlsb)
-  meta.io.state_req.bits.data.tag := UFix(0) // don't care
-  meta.io.state_req.bits.data.valid := tag_match
-  meta.io.state_req.bits.data.dirty := tag_match
-  
-  // pending store data, also used for AMO RHS
-  val amoalu = new AMOALU
-  when (tag_hit && r_req_write && p_store_rdy || r_replay_amo) {
-    p_store_idx   := r_cpu_req_idx
-    p_store_type  := r_cpu_req_type
-    p_store_cmd   := r_cpu_req_cmd
-    p_store_data  := cpu_req_data
-  }
-  when (p_amo) {
-    p_store_data := amoalu.io.out
-  }
-
-  // miss handling
-  val mshr = new MSHRFile()
-  mshr.io.req_val := tag_miss && r_req_readwrite && (!dirty || wb_rdy) && (!r_req_write || replayer.io.sdq_enq.ready)
-  mshr.io.req_ppn := cpu_req_tag
-  mshr.io.req_idx := r_cpu_req_idx(indexmsb,indexlsb)
-  mshr.io.req_tag := r_cpu_req_tag
-  mshr.io.req_offset := r_cpu_req_idx(offsetmsb,0)
-  mshr.io.req_cmd := r_cpu_req_cmd
-  mshr.io.req_type := r_cpu_req_type
-  mshr.io.req_sdq_id := replayer.io.sdq_id
-  mshr.io.mem_resp_val := io.mem.resp_val && (~rr_count === UFix(0))
-  mshr.io.mem_resp_tag := io.mem.resp_tag
-  mshr.io.mem_req <> wb.io.refill_req
-  mshr.io.meta_req.bits.inner_req <> meta_arb.io.in(1).bits 
-  mshr.io.meta_req.ready := meta_arb.io.in(1).ready
-  meta_arb.io.in(1).valid := mshr.io.meta_req.valid
-  mshr.io.replay <> replayer.io.replay
-  replayer.io.sdq_enq.valid := tag_miss && r_req_write && (!dirty || wb_rdy) && mshr.io.req_rdy
-  replayer.io.sdq_enq.bits := cpu_req_data
-  data_arb.io.in(0).bits.idx := mshr.io.mem_resp_idx
-
-  // replays
-  val replay = replayer.io.data_req.bits
-  val stall_replay = r_replay_amo || p_amo || p_store_valid
-  val replay_val = replayer.io.data_req.valid && !stall_replay
-  val replay_rdy = data_arb.io.in(1).ready
-  data_arb.io.in(1).bits.offset := replay.offset(offsetmsb,ramindexlsb)
-  data_arb.io.in(1).bits.idx := replay.idx
-  data_arb.io.in(1).bits.rw := replay.cmd === M_XWR
-  data_arb.io.in(1).valid := replay_val
-  replayer.io.data_req.ready := replay_rdy && !stall_replay
-  r_replay_amo := replay_amo_val && replay_rdy && !stall_replay
-
-  // store write mask generation.
-  // assumes store replays are higher-priority than pending stores.
-  val maskgen = new StoreMaskGen
-  val store_offset = Mux(!replay_val, p_store_idx(offsetmsb,0), replay.offset)
-  maskgen.io.typ := Mux(!replay_val, p_store_type, replay.typ)
-  maskgen.io.addr := store_offset(offsetlsb-1,0)
-  val store_wmask_wide = maskgen.io.wmask << Cat(store_offset(ramindexlsb-1,offsetlsb), Bits(0, log2up(CPU_DATA_BITS/8))).toUFix
-  val store_data = Mux(!replay_val, p_store_data, replay.data)
-  val store_data_wide = Fill(MEM_DATA_BITS/CPU_DATA_BITS, store_data)
-  data_arb.io.in(1).bits.data := store_data_wide
-  data_arb.io.in(1).bits.wmask := store_wmask_wide
-  data_arb.io.in(2).bits.data := store_data_wide
-  data_arb.io.in(2).bits.wmask := store_wmask_wide
-
-  // load data subword mux/sign extension.
-  // subword loads are delayed by one cycle.
-  val loadgen = new LoadDataGen
-  val loadgen_use_replay = Reg(replay_val && replay_rdy)
-  loadgen.io.typ := Mux(loadgen_use_replay, Reg(replay.typ), r_cpu_req_type)
-  loadgen.io.addr := Mux(loadgen_use_replay, Reg(replay.offset), r_cpu_req_idx)(ramindexlsb-1,0)
-  loadgen.io.din := data.io.resp
-
-  amoalu.io.cmd := p_store_cmd
-  amoalu.io.typ := p_store_type
-  amoalu.io.lhs := loadgen.io.r_dout.toUFix
-  amoalu.io.rhs := p_store_data.toUFix
-
-  early_nack := early_tag_nack || early_load_nack || r_cpu_req_val && r_req_amo || replay_amo_val || r_replay_amo
-
-  // reset and flush unit
-  val flusher = new FlushUnit(lines)
-  val flushed = Reg(resetVal = Bool(true))
-  val flush_rdy = mshr.io.fence_rdy && wb_rdy && !p_store_valid
-  flushed := flushed && !r_cpu_req_val || r_cpu_req_val && r_req_flush && flush_rdy && flusher.io.req.ready
-  flusher.io.req.valid := r_cpu_req_val && r_req_flush && flush_rdy && !flushed
-  flusher.io.wb_req <> wb_arb.io.in(0)
-  flusher.io.meta_req.bits.inner_req <> meta_arb.io.in(0).bits 
-  flusher.io.meta_req.ready :=  meta_arb.io.in(0).ready
-  meta_arb.io.in(0).valid := flusher.io.meta_req.valid
-  flusher.io.meta_resp <> meta.io.resp
-  flusher.io.resp.ready := Bool(true) // we don't respond to flush requests
-
-  // we usually nack rather than reporting that the cache is not ready.
-  // fences and flushes are the exceptions.
-  val pending_fence = Reg(resetVal = Bool(false))
-  pending_fence := (r_cpu_req_val && r_req_fence || pending_fence) && !flush_rdy
-  val nack_hit   = p_store_match || r_req_write && !p_store_rdy
-  val nack_miss  = dirty && !wb_rdy || !mshr.io.req_rdy || r_req_write && !replayer.io.sdq_enq.ready
-  val nack_flush = !flush_rdy && (r_req_fence || r_req_flush) ||
-                   !flushed && r_req_flush
-  val nack = early_nack || r_req_readwrite && Mux(tag_match, nack_hit, nack_miss) || nack_flush
-
-  io.cpu.req_rdy   := flusher.io.req.ready && !(r_cpu_req_val_ && r_req_flush) && !pending_fence
-  io.cpu.resp_nack := r_cpu_req_val_ && !io.cpu.req_kill && nack
-  io.cpu.resp_val  := (tag_hit && !nack_hit && r_req_read) || replayer.io.cpu_resp_val
-  io.cpu.resp_replay := replayer.io.cpu_resp_val
-  io.cpu.resp_miss := tag_miss && !nack_miss && r_req_read
-  io.cpu.resp_tag  := Mux(replayer.io.cpu_resp_val, replayer.io.cpu_resp_tag, r_cpu_req_tag)
-  io.cpu.resp_data := loadgen.io.dout
-  io.cpu.resp_data_subword := loadgen.io.r_dout_subword
-                      
-  wb.io.mem_req.ready := io.mem.req_rdy
-  io.mem.req_val   := wb.io.mem_req.valid
-  io.mem.req_rw    := wb.io.mem_req.bits.rw
-  io.mem.req_wdata := wb.io.mem_req_data
-  io.mem.req_tag   := wb.io.mem_req.bits.tag.toUFix
-  io.mem.req_addr  := wb.io.mem_req.bits.addr
+// interface between D$ and next level in memory hierarchy
+class ioDCache(view: List[String] = null) extends Bundle(view) {
+  val req_addr  = UFix(PADDR_BITS - OFFSET_BITS, INPUT);
+  val req_tag   = UFix(DMEM_TAG_BITS, INPUT);
+  val req_val   = Bool(INPUT);
+  val req_rdy   = Bool(OUTPUT);
+  val req_wdata = Bits(MEM_DATA_BITS, INPUT);
+  val req_rw    = Bool(INPUT);
+  val resp_data = Bits(MEM_DATA_BITS, OUTPUT);
+  val resp_tag  = Bits(DMEM_TAG_BITS, OUTPUT);
+  val resp_val  = Bool(OUTPUT);
 }
  
-class HellaCacheAssoc extends Component {
-  val io = new ioDCacheHella()
+class HellaCache extends Component {
+  val io = new Bundle {
+    val cpu = new ioDmem()
+    val mem = new ioDCache().flip
+  }
  
   val lines       = 1 << IDX_BITS
   val addrbits    = PADDR_BITS
diff --git a/rocket/src/main/scala/top.scala b/rocket/src/main/scala/top.scala
index 2e5e0311..605f882c 100644
--- a/rocket/src/main/scala/top.scala
+++ b/rocket/src/main/scala/top.scala
@@ -17,7 +17,7 @@ class Top() extends Component {
   val cpu       = new rocketProc();
   val icache    = new rocketICache(128, 2); // 128 sets x 2 ways
   val icache_pf = new rocketIPrefetcher();
-  val dcache    = new HellaCacheAssoc();
+  val dcache    = new HellaCache();
   val arbiter   = new rocketMemArbiter();
 
   arbiter.io.mem    <> io.mem; 
@@ -37,9 +37,9 @@ class Top() extends Component {
 object top_main {
   def main(args: Array[String]) = { 
     // Can turn off --debug and --vcd when done with debugging to improve emulator performance
-//    val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
+    val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
 //    val cpu_args = args ++ Array("--target-dir", "generated-src", "--debug");
-    val cpu_args = args ++ Array("--target-dir", "generated-src");
+//    val cpu_args = args ++ Array("--target-dir", "generated-src");
     // Set variables based off of command flags
 //     for(a <- args) {
 //         a match {