merge data wmask bugfix
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fd8f6ff026
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@ -648,7 +648,9 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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amoalu.io.rhs := data_buffer.head // default
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def mergeDataPut(beat: UInt, wmask: UInt, put_data: UInt) {
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data_buffer(beat) := ~wmask & data_buffer(beat) | wmask & put_data
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val full = FillInterleaved(8, wmask)
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data_buffer(beat) := (~full & data_buffer(beat)) | (full & put_data)
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wmask_buffer(beat) := wmask | wmask_buffer(beat)
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}
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def mergeData(dataBits: Int)(beat: UInt, incoming: UInt) {
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@ -656,10 +658,10 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val new_data = data_buffer(beat) // Newly Put data is already in the buffer
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amoalu.io.lhs := old_data >> xact.amo_shift_bits()
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amoalu.io.rhs := new_data >> xact.amo_shift_bits()
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val valid_beat = (xact.is(Acquire.putBlockType) || xact.addr_beat === beat)
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val wmask = Fill(dataBits, valid_beat) & wmask_buffer(beat)
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val valid_beat = (xact.isBuiltInType(Acquire.putBlockType) || xact.addr_beat === beat)
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val wmask = Fill(dataBits, valid_beat) & FillInterleaved(8, wmask_buffer(beat))
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data_buffer(beat) := ~wmask & old_data |
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wmask & Mux(xact.is(Acquire.putAtomicType),
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wmask & Mux(xact.isBuiltInType(Acquire.putAtomicType),
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amoalu.io.out << xact.amo_shift_bits(),
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new_data)
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when(xact.is(Acquire.putAtomicType) && valid_beat) { amo_result := old_data }
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@ -952,7 +954,6 @@ class L2AcquireTracker(trackerId: Int, bankId: Int) extends L2XactTracker {
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val beat = io.iacq().addr_beat
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when(io.iacq().hasData()) {
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mergeDataPut(beat, io.iacq().wmask(), io.iacq().data)
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wmask_buffer(beat) := io.iacq().wmask() | wmask_buffer(beat)
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//iacq_data_valid(beat) := Bool(true)
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pending_writes := pending_writes | UIntToOH(io.iacq().addr_beat)
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}
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@ -106,10 +106,11 @@ class Acquire extends ClientToManagerChannel
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def amo_shift_bits(dummy: Int = 0) = UInt(amoAluOperandBits)*amo_offset()
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def wmask(dummy: Int = 0) =
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Mux(isBuiltInType(Acquire.putAtomicType),
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FillInterleaved(amoAluOperandBits, UIntToOH(amo_offset())),
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FillInterleaved(amoAluOperandBits/8, UIntToOH(amo_offset())),
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Mux(isBuiltInType(Acquire.putBlockType) || isBuiltInType(Acquire.putType),
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FillInterleaved(8, union(tlWriteMaskBits, 1)),
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UInt(0, width = tlDataBits)))
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union(tlWriteMaskBits, 1),
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UInt(0, width = tlWriteMaskBits)))
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def full_wmask(dummy: Int = 0) = FillInterleaved(8, wmask())
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def addr(dummy: Int = 0) = Cat(this.addr_block, this.addr_beat, this.addr_byte())
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