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coreplex: allow zero interrupt sink/sources

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This commit is contained in:
Henry Cook 2016-11-16 16:49:10 -08:00
parent 479bc82f03
commit 24e3216fcf
3 changed files with 8 additions and 5 deletions
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4
src/main/scala/coreplex/BaseCoreplex.scala
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@ -58,9 +58,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
val cbus_beatBytes = p(XLen)/8 val cbus_beatBytes = p(XLen)/8
val cbus_lineBytes = l1tol2_lineBytes val cbus_lineBytes = l1tol2_lineBytes
val intBar = LazyModule(new IntXbar)
val mmio = TLOutputNode() val mmio = TLOutputNode()
val mmioInt = IntInputNode() val mmioInt = IntInputNode()
intBar.intnode := mmioInt
cbus.node := cbus.node :=
TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
TLWidthWidget(l1tol2_beatBytes)( TLWidthWidget(l1tol2_beatBytes)(

3
src/main/scala/coreplex/RISCVPlatform.scala
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@ -25,8 +25,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node) clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
plic.intnode := mmioInt plic.intnode := intBar.intnode
} }
trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle { trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {

6
src/main/scala/uncore/tilelink2/IntNodes.scala
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@ -41,7 +41,7 @@ case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
// The interrupts mapping must not overlap // The interrupts mapping must not overlap
sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) } sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) }
// The interrupts must perfectly cover the range // The interrupts must perfectly cover the range
require (sources.map(_.range.end).max == num) require (sources.isEmpty || sources.map(_.range.end).max == num)
} }
case class IntSinkPortParameters(sinks: Seq[IntSinkParameters]) case class IntSinkPortParameters(sinks: Seq[IntSinkParameters])
@ -57,7 +57,7 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
Vec(eo.size, Vec(eo.map(_.source.num).max, Bool())) Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
} }
def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = { def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = {
require (!ei.isEmpty) if (ei.isEmpty) Vec(0, Vec(0, Bool())) else
Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())) Vec(ei.size, Vec(ei.map(_.source.num).max, Bool()))
} }
@ -103,7 +103,7 @@ case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(IntS
class IntXbar extends LazyModule class IntXbar extends LazyModule
{ {
val intnode = IntAdapterNode( val intnode = IntAdapterNode(
numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink? numSourcePorts = 0 to 128,
numSinkPorts = 0 to 128, numSinkPorts = 0 to 128,
sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) }, sinkFn = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
sourceFn = { seq => sourceFn = { seq =>