From 24e3216fcfcab59ec6a679049e58e6a8fb0cedf1 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Wed, 16 Nov 2016 16:49:10 -0800
Subject: [PATCH] coreplex: allow zero interrupt sink/sources

---
 src/main/scala/coreplex/BaseCoreplex.scala     | 4 ++++
 src/main/scala/coreplex/RISCVPlatform.scala    | 3 +--
 src/main/scala/uncore/tilelink2/IntNodes.scala | 6 +++---
 3 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/coreplex/BaseCoreplex.scala b/src/main/scala/coreplex/BaseCoreplex.scala
index c7fdf950..1111ab1d 100644
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@@ -58,9 +58,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   val cbus_beatBytes = p(XLen)/8
   val cbus_lineBytes = l1tol2_lineBytes
 
+  val intBar = LazyModule(new IntXbar)
+
   val mmio = TLOutputNode()
   val mmioInt = IntInputNode()
 
+  intBar.intnode := mmioInt
+
   cbus.node :=
     TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
     TLWidthWidget(l1tol2_beatBytes)(
diff --git a/src/main/scala/coreplex/RISCVPlatform.scala b/src/main/scala/coreplex/RISCVPlatform.scala
index dc4fefcc..952de6a0 100644
--- a/src/main/scala/coreplex/RISCVPlatform.scala
+++ b/src/main/scala/coreplex/RISCVPlatform.scala
@@ -25,8 +25,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
   plic.node  := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
   clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
 
-  plic.intnode := mmioInt
-
+  plic.intnode := intBar.intnode
 }
 
 trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {
diff --git a/src/main/scala/uncore/tilelink2/IntNodes.scala b/src/main/scala/uncore/tilelink2/IntNodes.scala
index d98e93e7..86d441b7 100644
--- a/src/main/scala/uncore/tilelink2/IntNodes.scala
+++ b/src/main/scala/uncore/tilelink2/IntNodes.scala
@@ -41,7 +41,7 @@ case class IntSourcePortParameters(sources: Seq[IntSourceParameters])
   // The interrupts mapping must not overlap
   sources.map(_.range).combinations(2).foreach { case Seq(a, b) => require (!a.overlaps(b)) }
   // The interrupts must perfectly cover the range
-  require (sources.map(_.range.end).max == num)
+  require (sources.isEmpty || sources.map(_.range.end).max == num)
 }
 
 case class IntSinkPortParameters(sinks: Seq[IntSinkParameters])
@@ -57,7 +57,7 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
     Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
   }
   def bundleI(ei: Seq[IntEdge]): Vec[Vec[Bool]] = {
-    require (!ei.isEmpty)
+    if (ei.isEmpty) Vec(0, Vec(0, Bool())) else
     Vec(ei.size, Vec(ei.map(_.source.num).max, Bool()))
   }
 
@@ -103,7 +103,7 @@ case class IntInternalInputNode(num: Int) extends InternalInputNode(IntImp)(IntS
 class IntXbar extends LazyModule
 {
   val intnode = IntAdapterNode(
-    numSourcePorts = 1 to 1, // does it make sense to have more than one interrupt sink?
+    numSourcePorts = 0 to 128,
     numSinkPorts   = 0 to 128,
     sinkFn         = { _ => IntSinkPortParameters(Seq(IntSinkParameters())) },
     sourceFn       = { seq =>