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coreplex: allow zero interrupt sink/sources

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This commit is contained in:
Henry Cook
2016-11-16 16:49:10 -08:00
parent 479bc82f03
commit 24e3216fcf
3 changed files with 8 additions and 5 deletions
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src/main/scala/coreplex/RISCVPlatform.scala
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@ -25,8 +25,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
plic.intnode := mmioInt
plic.intnode := intBar.intnode
}
trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {