coreplex: allow zero interrupt sink/sources

src/main/scala/coreplex/BaseCoreplex.scala

@@ -58,9 +58,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
   val cbus_beatBytes = p(XLen)/8
   val cbus_lineBytes = l1tol2_lineBytes
 
+  val intBar = LazyModule(new IntXbar)
+
   val mmio = TLOutputNode()
   val mmioInt = IntInputNode()
 
+  intBar.intnode := mmioInt
+
   cbus.node :=
     TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
     TLWidthWidget(l1tol2_beatBytes)(