coreplex: allow zero interrupt sink/sources

2016-11-16 16:49:10 -08:00
parent 479bc82f03
commit 24e3216fcf
3 changed files with 8 additions and 5 deletions
--- a/src/main/scala/coreplex/BaseCoreplex.scala
+++ b/src/main/scala/coreplex/BaseCoreplex.scala
@ -58,9 +58,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
  val cbus_beatBytes = p(XLen)/8
  val cbus_lineBytes = l1tol2_lineBytes

+  val intBar = LazyModule(new IntXbar)
+
  val mmio = TLOutputNode()
  val mmioInt = IntInputNode()

+  intBar.intnode := mmioInt
+
  cbus.node :=
    TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
    TLWidthWidget(l1tol2_beatBytes)(