riscv/rocket-chip
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coreplex: allow zero interrupt sink/sources

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This commit is contained in:
Henry Cook
2016-11-16 16:49:10 -08:00
parent 479bc82f03
commit 24e3216fcf
3 changed files with 8 additions and 5 deletions
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4
src/main/scala/coreplex/BaseCoreplex.scala
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@ -58,9 +58,13 @@ trait CoreplexNetwork extends HasCoreplexParameters {
val cbus_beatBytes = p(XLen)/8
val cbus_lineBytes = l1tol2_lineBytes
val intBar = LazyModule(new IntXbar)
val mmio = TLOutputNode()
val mmioInt = IntInputNode()
intBar.intnode := mmioInt
cbus.node :=
TLAtomicAutomata(arithmetic = true)( // disable once TLB uses TL2 metadata
TLWidthWidget(l1tol2_beatBytes)(

3
src/main/scala/coreplex/RISCVPlatform.scala
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@ -25,8 +25,7 @@ trait CoreplexRISCVPlatform extends CoreplexNetwork {
plic.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
clint.node := TLFragmenter(cbus_beatBytes, cbus_lineBytes)(cbus.node)
plic.intnode := mmioInt
plic.intnode := intBar.intnode
}
trait CoreplexRISCVPlatformBundle extends CoreplexNetworkBundle {