Refining tilelink interface
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@ -39,12 +39,12 @@ class TransactionFinish extends Bundle {
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}
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class ioTileLink extends Bundle {
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val xact_init = new TransactionInit().asOutput
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val xact_abort = new TransactionAbort().asInput
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val probe_req = new ProbeRequest().asInput
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val probe_rep = new ProbeReply().asOutput
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val xact_rep = new TransactionReply().asInput
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val xact_finish = new TransactionFinish().asOutput
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val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
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val xact_abort = (new ioDecoupled) { new TransactionAbort() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
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}
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trait CoherencePolicy {
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@ -130,4 +130,6 @@ trait FourStateCoherence extends CoherencePolicy {
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}
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}
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}
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@ -174,8 +174,11 @@ object Constants
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require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
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// coherence parameters
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val TILE_XACT_ID_BITS = 1; // log2(NMSHR)
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val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set
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val NTILES = 1
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val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
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val TILE_ID_BITS = 1
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val TILE_XACT_ID_BITS = 1 // log2(NMSHR)
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val GLOBAL_XACT_ID_BITS = IDX_BITS // if one active xact per set
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val TTYPE_BITS = 2
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val X_READ_SHARED = UFix(0, TTYPE_BITS)
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