From 24a32c28113bd46846dfc0a64d82a5805696c2ed Mon Sep 17 00:00:00 2001
From: Henry Cook <hcook@s144.Millennium.Berkeley.EDU>
Date: Wed, 22 Feb 2012 12:14:57 -0800
Subject: [PATCH] Refining tilelink interface

---
 rocket/src/main/scala/coherence.scala | 14 ++++++++------
 rocket/src/main/scala/consts.scala    |  7 +++++--
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/rocket/src/main/scala/coherence.scala b/rocket/src/main/scala/coherence.scala
index 9fcf32eb..cfde62ba 100644
--- a/rocket/src/main/scala/coherence.scala
+++ b/rocket/src/main/scala/coherence.scala
@@ -39,12 +39,12 @@ class TransactionFinish extends Bundle {
 }
 
 class ioTileLink extends Bundle { 
-  val xact_init   = new TransactionInit().asOutput
-  val xact_abort  = new TransactionAbort().asInput
-  val probe_req   = new ProbeRequest().asInput
-  val probe_rep   = new ProbeReply().asOutput
-  val xact_rep    = new TransactionReply().asInput
-  val xact_finish = new TransactionFinish().asOutput
+  val xact_init   = (new ioDecoupled) { new TransactionInit() }.flip
+  val xact_abort  = (new ioDecoupled) { new TransactionAbort() }
+  val probe_req   = (new ioDecoupled) { new ProbeRequest() }
+  val probe_rep   = (new ioDecoupled) { new ProbeReply() }.flip
+  val xact_rep    = (new ioDecoupled) { new TransactionReply() }
+  val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
 }
 
 trait CoherencePolicy {
@@ -130,4 +130,6 @@ trait FourStateCoherence extends CoherencePolicy {
   }
 }
 
+
+
 }
diff --git a/rocket/src/main/scala/consts.scala b/rocket/src/main/scala/consts.scala
index 34071842..e2ce4cce 100644
--- a/rocket/src/main/scala/consts.scala
+++ b/rocket/src/main/scala/consts.scala
@@ -174,8 +174,11 @@ object Constants
   require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
 
   // coherence parameters
-  val TILE_XACT_ID_BITS = 1; // log2(NMSHR)
-  val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set
+  val NTILES = 1
+  val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8 
+  val TILE_ID_BITS = 1
+  val TILE_XACT_ID_BITS = 1 // log2(NMSHR)
+  val GLOBAL_XACT_ID_BITS = IDX_BITS // if one active xact per set
 
   val TTYPE_BITS = 2
   val X_READ_SHARED    = UFix(0, TTYPE_BITS)