riscv/rocket-chip
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Refining tilelink interface

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This commit is contained in:
Henry Cook 2012-02-22 12:14:57 -08:00
parent 18bd0c232b
commit 24a32c2811
2 changed files with 13 additions and 8 deletions
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14
rocket/src/main/scala/coherence.scala
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@ -39,12 +39,12 @@ class TransactionFinish extends Bundle {
} }
class ioTileLink extends Bundle { class ioTileLink extends Bundle {
val xact_init = new TransactionInit().asOutput val xact_init = (new ioDecoupled) { new TransactionInit() }.flip
val xact_abort = new TransactionAbort().asInput val xact_abort = (new ioDecoupled) { new TransactionAbort() }
val probe_req = new ProbeRequest().asInput val probe_req = (new ioDecoupled) { new ProbeRequest() }
val probe_rep = new ProbeReply().asOutput val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
val xact_rep = new TransactionReply().asInput val xact_rep = (new ioDecoupled) { new TransactionReply() }
val xact_finish = new TransactionFinish().asOutput val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
} }
trait CoherencePolicy { trait CoherencePolicy {
@ -130,4 +130,6 @@ trait FourStateCoherence extends CoherencePolicy {
} }
} }
} }

7
rocket/src/main/scala/consts.scala
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@ -174,8 +174,11 @@ object Constants
require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS); require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
// coherence parameters // coherence parameters
val TILE_XACT_ID_BITS = 1; // log2(NMSHR) val NTILES = 1
val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
val TILE_ID_BITS = 1
val TILE_XACT_ID_BITS = 1 // log2(NMSHR)
val GLOBAL_XACT_ID_BITS = IDX_BITS // if one active xact per set
val TTYPE_BITS = 2 val TTYPE_BITS = 2
val X_READ_SHARED = UFix(0, TTYPE_BITS) val X_READ_SHARED = UFix(0, TTYPE_BITS)