riscv/rocket-chip
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Refining tilelink interface

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Henry Cook committed 2012-02-22 12:15:47 -08:00
1 parent 18bd0c232b
commit 24a32c2811
2 files changed
+13 -8
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rocket/src/main/scala/consts.scala
+5 -2
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@@ -174,8 +174,11 @@ object Constants
require(IDX_BITS+OFFSET_BITS <= PGIDX_BITS);
// coherence parameters
val TILE_XACT_ID_BITS = 1; // log2(NMSHR)
val GLOBAL_XACT_ID_BITS = IDX_BITS; // if one active xact per set
val NTILES = 1
val COHERENCE_DATA_BITS = (1 << OFFSET_BITS)*8
val TILE_ID_BITS = 1
val TILE_XACT_ID_BITS = 1 // log2(NMSHR)
val GLOBAL_XACT_ID_BITS = IDX_BITS // if one active xact per set
val TTYPE_BITS = 2
val X_READ_SHARED = UFix(0, TTYPE_BITS)