riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Reduce FMA pipeline depths

Browse Source 
FMA QoR has improved enough to allow this change.
This commit is contained in:
Andrew Waterman 2013-10-25 15:27:24 -07:00
parent 1583560757
commit 23f7bab4f3
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
rocket/src/main/scala/core.scala
View File

@ -21,7 +21,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
val dpath = Module(new Datapath) val dpath = Module(new Datapath)
val fpu: FPU = if (conf.fpu) { val fpu: FPU = if (conf.fpu) {
val fpu = Module(new FPU(4,6)) val fpu = Module(new FPU(2,3))
dpath.io.fpu <> fpu.io.dpath dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl ctrl.io.fpu <> fpu.io.ctrl
fpu.io.sfma.valid := Bool(false) // hook these up to coprocessor? fpu.io.sfma.valid := Bool(false) // hook these up to coprocessor?