riscv/rocket-chip
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Reduce FMA pipeline depths

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FMA QoR has improved enough to allow this change.
This commit is contained in:
Andrew Waterman
2013-10-25 15:27:24 -07:00
parent 1583560757
commit 23f7bab4f3
1 changed files with 1 additions and 1 deletions
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rocket/src/main/scala/core.scala
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@@ -21,7 +21,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
val dpath = Module(new Datapath)
val fpu: FPU = if (conf.fpu) {
val fpu = Module(new FPU(4,6))
val fpu = Module(new FPU(2,3))
dpath.io.fpu <> fpu.io.dpath
ctrl.io.fpu <> fpu.io.ctrl
fpu.io.sfma.valid := Bool(false) // hook these up to coprocessor?