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tilelink2 AddressDecoder: validate output of optimization

This commit is contained in:
Wesley W. Terpstra 2016-09-16 00:49:05 -07:00
parent 023a54f122
commit 2210e71f42
2 changed files with 16 additions and 2 deletions

View File

@ -28,11 +28,22 @@ object AddressDecoder
require (!a.overlaps(b)) // it must be possible to disambiguate ports! require (!a.overlaps(b)) // it must be possible to disambiguate ports!
} } } }
} }
val maxBits = log2Ceil(ports.map(_.map(_.max).max).max + 1) val maxBits = log2Ceil(ports.map(_.map(_.max).max).max + 1)
val bits = (0 until maxBits).map(BigInt(1) << _).toSeq val bits = (0 until maxBits).map(BigInt(1) << _).toSeq
val selected = recurse(Seq(ports.map(_.sorted).sorted(portOrder)), bits) val selected = recurse(Seq(ports.map(_.sorted).sorted(portOrder)), bits)
selected.reduceLeft(_ | _) val output = selected.reduceLeft(_ | _)
// port validation via mask expansion
// Modify the AddressSets to allow the new wider match functions
val widePorts = ports.map { _.map { _.widen(~output) } }
// Verify that it remains possible to disambiguate all ports
widePorts.combinations(2).foreach { case Seq(x, y) =>
x.foreach { a => y.foreach { b =>
require (!a.overlaps(b))
} }
}
output
} }
// A simpler version that works for a Seq[Int] // A simpler version that works for a Seq[Int]

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@ -98,6 +98,9 @@ case class AddressSet(base: BigInt, mask: BigInt) extends Ordered[AddressSet]
// A strided slave serves discontiguous ranges // A strided slave serves discontiguous ranges
def strided = alignment1 != mask def strided = alignment1 != mask
// Widen the match function to ignore all bits in imask
def widen(imask: BigInt) = AddressSet(base & ~imask, mask | imask)
// AddressSets have one natural Ordering (the containment order) // AddressSets have one natural Ordering (the containment order)
def compare(x: AddressSet) = { def compare(x: AddressSet) = {
val primary = (this.base - x.base).signum // smallest address first val primary = (this.base - x.base).signum // smallest address first