interrupts: implement in crossing wrapper
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c6f95570df
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@ -6,11 +6,13 @@ import Chisel._
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import freechips.rocketchip.config._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.interrupts._
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trait HasCrossingHelper extends LazyScope
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trait HasCrossingHelper extends LazyScope
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{
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{
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this: LazyModule =>
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this: LazyModule =>
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val crossing: CoreplexClockCrossing
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val crossing: CoreplexClockCrossing
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def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
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def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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crossing match {
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crossing match {
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@ -32,7 +34,7 @@ trait HasCrossingHelper extends LazyScope
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sink.node
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sink.node
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}
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}
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case AsynchronousCrossing(depth, sync) => {
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case AsynchronousCrossing(depth, sync) => {
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def sourceGen = this { LazyModule(new TLAsyncCrossingSource(sync)) }
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def sourceGen = LazyModule(new TLAsyncCrossingSource(sync))
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def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
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def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
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val source = if (out) this { sourceGen } else sourceGen
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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val sink = if (out) sinkGen else this { sinkGen }
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@ -44,8 +46,45 @@ trait HasCrossingHelper extends LazyScope
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}
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}
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}
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}
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}
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}
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// def cross(x: IntCrossableNode, name: String): IntOutwardNode = { x.node }
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def cross(x: IntCrossableNode, name: String, alreadyRegistered: Boolean = false): IntOutwardNode = {
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val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
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crossing match {
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case SynchronousCrossing(_) => {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(0))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "SyncSource")
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sink.suggestName(name + "SyncSink")
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source.node := x.node
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sink.node := source.node
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sink.node
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}
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case RationalCrossing(_) => {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(1))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "SyncSource")
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sink.suggestName(name + "SyncSink")
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source.node := x.node
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sink.node := source.node
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sink.node
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}
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case AsynchronousCrossing(_, sync) => {
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def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
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def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
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val source = if (out) this { sourceGen } else sourceGen
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val sink = if (out) sinkGen else this { sinkGen }
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source.suggestName(name + "SyncSource")
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sink.suggestName(name + "SyncSink")
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source.node := x.node
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sink.node := source.node
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sink.node
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}
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}
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}
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}
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}
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class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossingHelper
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class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossingHelper
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@ -18,3 +18,41 @@ class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
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}
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}
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}
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}
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}
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}
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object IntSyncCrossingSource
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{
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def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSource(alreadyRegistered)).node
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}
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class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
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{
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val node = IntSyncSourceNode()
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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if (alreadyRegistered) {
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out.sync := in
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} else {
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out.sync := RegNext(in)
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}
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}
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}
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}
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class IntSyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
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{
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val node = IntSyncSinkNode()
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lazy val module = new LazyModuleImp(this) {
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(node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
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out := SynchronizerShiftReg(in.sync, sync)
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}
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}
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}
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object IntSyncCrossingSink
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{
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def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSink(sync)).node
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}
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