From 217575805060f09330b6588df136918a081b2a71 Mon Sep 17 00:00:00 2001
From: "Wesley W. Terpstra" <wesley@sifive.com>
Date: Thu, 19 Oct 2017 22:19:19 -0700
Subject: [PATCH] interrupts: implement in crossing wrapper

---
 src/main/scala/coreplex/CrossingWrapper.scala | 45 +++++++++++++++++--
 src/main/scala/interrupts/Crossing.scala      | 38 ++++++++++++++++
 2 files changed, 80 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/coreplex/CrossingWrapper.scala b/src/main/scala/coreplex/CrossingWrapper.scala
index d6508a3f..3d483327 100644
--- a/src/main/scala/coreplex/CrossingWrapper.scala
+++ b/src/main/scala/coreplex/CrossingWrapper.scala
@@ -6,11 +6,13 @@ import Chisel._
 import freechips.rocketchip.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
+import freechips.rocketchip.interrupts._
 
 trait HasCrossingHelper extends LazyScope
 {
   this: LazyModule =>
   val crossing: CoreplexClockCrossing
+
   def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
     val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
     crossing match {
@@ -32,7 +34,7 @@ trait HasCrossingHelper extends LazyScope
         sink.node
       }
       case AsynchronousCrossing(depth, sync) => {
-        def sourceGen = this { LazyModule(new TLAsyncCrossingSource(sync)) }
+        def sourceGen = LazyModule(new TLAsyncCrossingSource(sync))
         def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
         val source = if (out) this { sourceGen } else sourceGen
         val sink = if (out) sinkGen else this { sinkGen }
@@ -44,8 +46,45 @@ trait HasCrossingHelper extends LazyScope
       }
     }
   }
-  // def cross(x: IntCrossableNode, name: String): IntOutwardNode = { x.node }
+
+  def cross(x: IntCrossableNode, name: String, alreadyRegistered: Boolean = false): IntOutwardNode = {
+    val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
+    crossing match {
+      case SynchronousCrossing(_) => {
+        def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
+        def sinkGen = LazyModule(new IntSyncCrossingSink(0))
+        val source = if (out) this { sourceGen } else sourceGen
+        val sink = if (out) sinkGen else this { sinkGen }
+        source.suggestName(name + "SyncSource")
+        sink.suggestName(name + "SyncSink")
+        source.node := x.node
+        sink.node := source.node
+        sink.node
+      }
+      case RationalCrossing(_) => {
+        def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
+        def sinkGen = LazyModule(new IntSyncCrossingSink(1))
+        val source = if (out) this { sourceGen } else sourceGen
+        val sink = if (out) sinkGen else this { sinkGen }
+        source.suggestName(name + "SyncSource")
+        sink.suggestName(name + "SyncSink")
+        source.node := x.node
+        sink.node := source.node
+        sink.node
+      }
+      case AsynchronousCrossing(_, sync) => {
+        def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
+        def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
+        val source = if (out) this { sourceGen } else sourceGen
+        val sink = if (out) sinkGen else this { sinkGen }
+        source.suggestName(name + "SyncSource")
+        sink.suggestName(name + "SyncSink")
+        source.node := x.node
+        sink.node := source.node
+        sink.node
+      }
+    }
+  }
 }
 
 class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossingHelper
-
diff --git a/src/main/scala/interrupts/Crossing.scala b/src/main/scala/interrupts/Crossing.scala
index 67ba2075..5c3f8568 100644
--- a/src/main/scala/interrupts/Crossing.scala
+++ b/src/main/scala/interrupts/Crossing.scala
@@ -18,3 +18,41 @@ class IntXing(sync: Int = 3)(implicit p: Parameters) extends LazyModule
     }
   }
 }
+
+object IntSyncCrossingSource
+{
+  def apply(alreadyRegistered: Boolean = false)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSource(alreadyRegistered)).node
+}
+
+
+class IntSyncCrossingSource(alreadyRegistered: Boolean = false)(implicit p: Parameters) extends LazyModule
+{
+  val node = IntSyncSourceNode()
+
+  lazy val module = new LazyModuleImp(this) {
+    (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
+      if (alreadyRegistered) {
+        out.sync := in
+      } else {
+        out.sync := RegNext(in)
+      }
+    }
+  }
+}
+
+
+class IntSyncCrossingSink(sync: Int = 3)(implicit p: Parameters) extends LazyModule
+{
+  val node = IntSyncSinkNode()
+
+  lazy val module = new LazyModuleImp(this) {
+    (node.in zip node.out) foreach { case ((in, edgeIn), (out, edgeOut)) =>
+      out := SynchronizerShiftReg(in.sync, sync)
+    }
+  }
+}
+
+object IntSyncCrossingSink
+{
+  def apply(sync: Int = 3)(implicit p: Parameters) = LazyModule(new IntSyncCrossingSink(sync)).node
+}