riscv/rocket-chip
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interrupts: implement in crossing wrapper

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This commit is contained in:
Wesley W. Terpstra
2017-10-19 22:19:19 -07:00
parent c6f95570df
commit 2175758050
2 changed files with 80 additions and 3 deletions
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45
src/main/scala/coreplex/CrossingWrapper.scala
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@@ -6,11 +6,13 @@ import Chisel._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
trait HasCrossingHelper extends LazyScope
{
this: LazyModule =>
val crossing: CoreplexClockCrossing
def cross(x: TLCrossableNode, name: String): TLOutwardNode = {
val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
crossing match {
@@ -32,7 +34,7 @@ trait HasCrossingHelper extends LazyScope
sink.node
}
case AsynchronousCrossing(depth, sync) => {
def sourceGen = this { LazyModule(new TLAsyncCrossingSource(sync)) }
def sourceGen = LazyModule(new TLAsyncCrossingSource(sync))
def sinkGen = LazyModule(new TLAsyncCrossingSink(depth, sync))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
@@ -44,8 +46,45 @@ trait HasCrossingHelper extends LazyScope
}
}
}
// def cross(x: IntCrossableNode, name: String): IntOutwardNode = { x.node }
def cross(x: IntCrossableNode, name: String, alreadyRegistered: Boolean = false): IntOutwardNode = {
val out = x.node.parentsOut.exists(_ eq this) // is the crossing exiting the wrapper?
crossing match {
case SynchronousCrossing(_) => {
def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
def sinkGen = LazyModule(new IntSyncCrossingSink(0))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "SyncSource")
sink.suggestName(name + "SyncSink")
source.node := x.node
sink.node := source.node
sink.node
}
case RationalCrossing(_) => {
def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
def sinkGen = LazyModule(new IntSyncCrossingSink(1))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "SyncSource")
sink.suggestName(name + "SyncSink")
source.node := x.node
sink.node := source.node
sink.node
}
case AsynchronousCrossing(_, sync) => {
def sourceGen = LazyModule(new IntSyncCrossingSource(alreadyRegistered))
def sinkGen = LazyModule(new IntSyncCrossingSink(sync))
val source = if (out) this { sourceGen } else sourceGen
val sink = if (out) sinkGen else this { sinkGen }
source.suggestName(name + "SyncSource")
sink.suggestName(name + "SyncSink")
source.node := x.node
sink.node := source.node
sink.node
}
}
}
}
class CrossingWrapper(val crossing: CoreplexClockCrossing)(implicit p: Parameters) extends SimpleLazyModule with HasCrossingHelper