riscv/rocket-chip
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Avoid chisel2 pitfall

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This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3.  D'oh.
This commit is contained in:
Andrew Waterman 2016-06-01 23:35:49 -07:00
parent 5629fb62bf
commit 20e1de08da
1 changed files with 2 additions and 2 deletions
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4
uncore/src/main/scala/debug.scala
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@ -417,7 +417,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
val haltnotStatus = Wire(Vec(numHaltnotStatus, Bits(width = 32))) val haltnotStatus = Wire(Vec(numHaltnotStatus, Bits(width = 32)))
val rdHaltnotStatus = Wire(Bits(width = 32)) val rdHaltnotStatus = Wire(Bits(width = 32))
val haltnotSummary = Vec(haltnotStatus.map(_.orR)).toBits val haltnotSummary = Cat(haltnotStatus.map(_.orR).reverse)
// --- Debug RAM // --- Debug RAM
@ -539,7 +539,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
} }
for (ii <- 0 until numHaltnotStatus) { for (ii <- 0 until numHaltnotStatus) {
haltnotStatus(ii) := Vec(haltnotRegs.slice(ii * 32, (ii + 1) * 32)).toBits haltnotStatus(ii) := Cat(haltnotRegs.slice(ii * 32, (ii + 1) * 32).reverse)
} }
//-------------------------------------------------------------- //--------------------------------------------------------------