From 20e1de08da5b998032f85b742b4df81da00626ba Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 1 Jun 2016 23:35:49 -0700
Subject: [PATCH] Avoid chisel2 pitfall

This code is erroneously flagged as incompatible with chisel3.
In fact, it is correct in both chisel2 and chisel3.  D'oh.
---
 uncore/src/main/scala/debug.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/uncore/src/main/scala/debug.scala b/uncore/src/main/scala/debug.scala
index 13fa1555..4cb24eb5 100644
--- a/uncore/src/main/scala/debug.scala
+++ b/uncore/src/main/scala/debug.scala
@@ -417,7 +417,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
   val haltnotStatus = Wire(Vec(numHaltnotStatus, Bits(width = 32)))
   val rdHaltnotStatus = Wire(Bits(width = 32))
 
-  val haltnotSummary = Vec(haltnotStatus.map(_.orR)).toBits
+  val haltnotSummary = Cat(haltnotStatus.map(_.orR).reverse)
 
   // --- Debug RAM
 
@@ -539,7 +539,7 @@ class DebugModule ()(implicit val p:cde.Parameters)
   }
 
   for (ii <- 0 until numHaltnotStatus) {
-    haltnotStatus(ii) := Vec(haltnotRegs.slice(ii * 32, (ii + 1) * 32)).toBits
+    haltnotStatus(ii) := Cat(haltnotRegs.slice(ii * 32, (ii + 1) * 32).reverse)
   }
 
   //--------------------------------------------------------------