riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Special cased NTILES == 1 due to log2up revision

Browse Source
This commit is contained in:
Henry Cook 2012-03-09 11:04:58 -08:00
parent 3a72ace057
commit 2014db41bd
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
uncore/coherence.scala
View File

@ -297,7 +297,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
val t_type_ = Reg{ Bits() } val t_type_ = Reg{ Bits() }
val init_tile_id_ = Reg{ Bits() } val init_tile_id_ = Reg{ Bits() }
val tile_xact_id_ = Reg{ Bits() } val tile_xact_id_ = Reg{ Bits() }
val p_rep_count = Reg(resetVal = UFix(0, width = log2up(NTILES))) val p_rep_count = if (NTILES == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2up(NTILES)))
val p_req_flags = Reg(resetVal = Bits(0, width = NTILES)) val p_req_flags = Reg(resetVal = Bits(0, width = NTILES))
val p_rep_tile_id_ = Reg{ Bits() } val p_rep_tile_id_ = Reg{ Bits() }
val x_needs_read = Reg(resetVal = Bool(false)) val x_needs_read = Reg(resetVal = Bool(false))
@ -346,7 +346,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init) x_init_data_needs_write := transactionInitHasData(io.alloc_req.bits.xact_init)
x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0)) x_needs_read := needsMemRead(io.alloc_req.bits.xact_init.t_type, UFix(0))
p_rep_count := UFix(NTILES-1) if(NTILES > 1) p_rep_count := UFix(NTILES-1)
p_req_flags := ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only p_req_flags := ~( UFix(1) << io.alloc_req.bits.tile_id ) //TODO: Broadcast only
mem_cnt := UFix(0) mem_cnt := UFix(0)
p_w_mem_cmd_sent := Bool(false) p_w_mem_cmd_sent := Bool(false)
@ -366,7 +366,7 @@ class XactTracker(id: Int) extends Component with FourStateCoherence {
when(io.p_rep_cnt_dec.orR) { when(io.p_rep_cnt_dec.orR) {
val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec) val p_rep_count_next = p_rep_count - PopCount(io.p_rep_cnt_dec)
io.pop_p_rep := io.p_rep_cnt_dec io.pop_p_rep := io.p_rep_cnt_dec
p_rep_count := p_rep_count_next if(NTILES > 1) p_rep_count := p_rep_count_next
when(p_rep_count === UFix(0)) { when(p_rep_count === UFix(0)) {
io.pop_p_rep := Bool(true) io.pop_p_rep := Bool(true)
state := s_mem state := s_mem