riscv/rocket-chip
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first cut at optimized state transitions

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This commit is contained in:
Henry Cook
2015-03-18 17:55:05 -07:00
parent 42aa4aa8ca
commit 1ff184bf62
2 changed files with 94 additions and 94 deletions
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19
uncore/src/main/scala/uncore.scala
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@ -151,12 +151,23 @@ abstract class XactTracker extends CoherenceAgentModule {
}
def addPendingBitWhenHasData[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[LogicalNetworkIO[T]]) = {
(Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.hasData()) &
UIntToOH(in.bits.payload.addr_beat))
Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.hasData()) &
UIntToOH(in.bits.payload.addr_beat)
}
def dropPendingBitWhenHasData[T <: HasTileLinkData with HasTileLinkBeatId](in: DecoupledIO[LogicalNetworkIO[T]]) = {
~Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.hasData()) |
~UIntToOH(in.bits.payload.addr_beat)
}
//TODO | with existing wmask_buffer?
def addPendingBitWhenWmaskIsNotFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
(Fill(in.bits.payload.tlDataBeats, in.fire() && !in.bits.payload.wmask().andR) &
UIntToOH(in.bits.payload.addr_beat))
Fill(in.bits.payload.tlDataBeats, in.fire() && !in.bits.payload.wmask().andR) &
UIntToOH(in.bits.payload.addr_beat)
}
def dropPendingBitWhenWmaskIsFull(in: DecoupledIO[LogicalNetworkIO[Acquire]]) = {
~Fill(in.bits.payload.tlDataBeats, in.fire() && in.bits.payload.wmask().andR) |
~UIntToOH(in.bits.payload.addr_beat)
}
}